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參數資料
| 型號： | ZL10038LDG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | MULTIMETER, DIGITAL; Accuracy, AC voltage range:+/-1.5% rdg + 3 digits; Accuracy, DC current range:+/-2.5% rdg + 3 digits; Accuracy, DC voltage range:+/-1.2% rdg + 3 digits; Accuracy, resistance range:+/-1.5%rdg + 3 digits; Current RoHS Compliant: NA |
| 中文描述： | 數字衛(wèi)星調諧器射頻旁路 |
| 文件頁數： | 19/38頁 |
| 文件大?。?/td> | 939K |
| 代理商： | ZL10038LDG |
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ZL10036
Data Sheet
19
Zarlink Semiconductor Inc.
2.7 Control Logic
The ZL10036 is controlled by an I2C data bus and can function as a slave receiver or slave transmitter compatible
with 3V3 or 5 V levels.
Data and Clock are input on the SDA and SCL lines respectively as defined by I2C bus standard. The device can
either accept data (slave receiver, write mode), or send data (slave transmitter, read mode). The LSB of the
address byte (R/W) sets the device into write mode if it is logic ‘0’, and read mode if it is logic ‘1’. Table 4 and Table
6 illustrate the format of the read and write data respectively. The device can be programmed to respond to one of
four addresses, which enables the use of more than one device in an I2C bus system if required for use in PVR
1
systems, for example. Table 3 shows how the address is selected by applying a voltage to the address, ‘
ADD
’,
input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and
during following acknowledge periods after further data bytes are received. When the device is programmed into
read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods
to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
All the ZL10036 functions are controlled by register bits written through the I2C bus interface. The
SLEEP
pin can
be used to power-down the device, but it can also be put into the power-down mode with the
PD
register bit, the two
functions being logically OR’ed.
Feedback on the status of the ZL10036 is provided through eight bits in the status byte register, and the phase lock
state is also available on the
LOCK
output pin (as well as the
FL
register bit).
3.0 User Control
3.1 I/O Pins
The I2C interface controls all the major functions in the ZL10036. Apart from the various analogue functions, the
only pins that either control the ZL10036, or are controlled by the internal logic, are the
LOCK
,
SLEEP
,
P1,
P0
and
ADD
pins. Details follow:
3.1.1 LOCK - Pin 25
This is an output which indicates phase frequency lock for optimum phase noise. The CMOS output can directly
drive a low power LED if required.
3.1.2 SLEEP - Pin 11
The
SLEEP
pin shuts down the analogue sections of the device to give a considerable power saving, typically
reducing the power to about one third of its normal level. The RF-bypass function is entirely separate and is
unaffected by the state of this pin. The
SLEEP
pin’s function is OR’ed with the
PD
register bit see 3.4.9, “Power
Down (PD Bit)“ on page 24, so that if either is a logic one, the ZL10036 will be powered down, or alternatively, both
must be at logic zero for normal operation.
3.1.3 Output Ports, P1 & P0 - Pins 39 & 24
Two open-collector ports are provided for general purpose use, under control of register bits
P1
and
P0
. The default
at power-up is for the
P1
&
P0
register bits to be low, hence the outputs will be off, i.e., in their high-impedance
states. If connected to a pull-up resistor this will therefore result in a logic high. Setting a register bit high will turn
the corresponding output on and therefore pull the logic level to near 0 V giving a logic low.
1. PVR - Personal Video Recorder where dual tuners allow the viewer to watch one channel and record another simultaneously, usually to a
hard-disk recording system.
相關PDF資料 |
PDF描述 |
|---|---|
| ZL10036 | Digital Satellite Tuner with RF Bypass |
| ZL10036LDF | Digital Satellite Tuner with RF Bypass |
| ZL10036LDF1 | Digital Satellite Tuner with RF Bypass |
| ZL10036LDG | Digital Satellite Tuner with RF Bypass |
| ZL10036LDG1 | Digital Satellite Tuner with RF Bypass |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ZL10039 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
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