- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373781 > ZL10038LDG (Zarlink Semiconductor Inc.) MULTIMETER, DIGITAL; Accuracy, AC voltage range:+/-1.5% rdg + 3 digits; Accuracy, DC current range:+/-2.5% rdg + 3 digits; Accuracy, DC voltage range:+/-1.2% rdg + 3 digits; Accuracy, resistance range:+/-1.5%rdg + 3 digits; Current RoHS Compliant: NA PDF資料下載
參數(shù)資料
| 型號： | ZL10038LDG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | MULTIMETER, DIGITAL; Accuracy, AC voltage range:+/-1.5% rdg + 3 digits; Accuracy, DC current range:+/-2.5% rdg + 3 digits; Accuracy, DC voltage range:+/-1.2% rdg + 3 digits; Accuracy, resistance range:+/-1.5%rdg + 3 digits; Current RoHS Compliant: NA |
| 中文描述： | 數(shù)字衛(wèi)星調(diào)諧器射頻旁路 |
| 文件頁數(shù)： | 23/38頁 |
| 文件大小： | 939K |
| 代理商： | ZL10038LDG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
ZL10036
Data Sheet
23
Zarlink Semiconductor Inc.
3.4.3 Synthesizer Division Ratio (2
14
:2
0
Bits)
The PLL synthesizer interfaces with the LO multiplex output and runs at the desired frequency for down-conversion.
The step size at the desired conversion frequency, is equal to the loop comparison frequency.
The programmable division ratio,
2
14
to
2
0
, required for a desired conversion frequency, can be calculated from the
following formula:
f
step
+
+
(
×
Desired conversion frequency =
where:
f
step
= Fcomp
3.4.4 RF Gain (RFG Bit)
The RF gain is programmed by setting the
RFG
bit, bit-5 of register byte-4 as required. See also Figure 4, “AGC
Control Structure” on page 13.
3.4.5 Baseband Pre-Filter Gain Adjust (BA1:0 Bits)
The baseband pre-filter gain is programmed by setting
BA1:0
, bits-4 & 3 of register byte-4 as required. See also
Figure 4, “AGC Control Structure” on page 13.
3.4.6 Baseband Post-Filter Gain (BG1:0 Bits)
The baseband post-filter gain is programmed by setting
BG1:0
, bits-2 & 1 of register byte-4 as required. See also
Figure 4, “AGC Control Structure” on page 13.
RFG
Gain Adjust (dB)
0
0
(reset state)
1
+4
Table 8 - RFG Register Bit Function
BA1
BA0
Pre-Filter Gain Adjust (dB)
0
0
0.0
(reset state)
0
1
+4.2
1
0
+8.4
1
1
+12.6
Table 9 - BA1/0 Register Bits Function
BG1
BG0
Post-Filter Gain Adjust (dB)
0
0
0.0
(reset state)
0
1
+4.2
1
0
+8.4
1
1
+12.6
Table 10 - BG1/0 Register Bits Function
2
14
2
13
2
12
2
2
2
1
+
→
2
0
+
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL10036 | Digital Satellite Tuner with RF Bypass |
| ZL10036LDF | Digital Satellite Tuner with RF Bypass |
| ZL10036LDF1 | Digital Satellite Tuner with RF Bypass |
| ZL10036LDG | Digital Satellite Tuner with RF Bypass |
| ZL10036LDG1 | Digital Satellite Tuner with RF Bypass |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10039 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。