參數資料
型號: ZL30102QDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網絡
英文描述: T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64
文件頁數: 17/50頁
文件大?。?/td> 481K
代理商: ZL30102QDG
ZL30102
Data Sheet
17
Zarlink Semiconductor Inc.
Figure 8 - Timing Diagram of Hitless Reference Switching
The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value
thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode.
(see Figure 9). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE
circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode.
This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the
input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30102 is
always hitless unless TIE_CLR is kept low continuously.
locked to REF1
REF0
Output
Clock
TIE_CLR = 1
TIE_CLR = 0
REF1
REF0
Output
Clock
REF1
locked to REF1
REF0
Output
Clock
REF1
REF0
Output
Clock
REF1
locked to REF0
locked to REF0
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