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參數(shù)資料
| 型號： | ZL30410 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CONN HDR INVERSE 30POS 5ROW VERT |
| 中文描述： | 多業(yè)務(wù)線卡鎖相環(huán) |
| 文件頁數(shù)： | 13/38頁 |
| 文件大小： | 400K |
| 代理商： | ZL30410 |
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ZL30410
Data Sheet
13
Zarlink Semiconductor Inc.
Holdover State (Holdover Mode)
The Holdover State is typically entered for a short duration while synchronization with the network is temporarily
disrupted. In Holdover Mode, the ZL30410 generates clocks, which are not locked to an external reference signal
but their frequencies are based on stored coefficients in memory that were determined while the PLL was in Normal
Mode and locked to an external reference signal.
The initial frequency offset of the ZL30410 in Holdover Mode is 70x10
-12
. This is more accurate than Telcordia’s
GR-1244-CORE Stratum 3E requirement of +1x10
-9
. When the ZL30410 is transitioned into Holdover Mode,
holdover stability is determined by the stability of the 20 MHz Master Clock Oscillator. Selection of the oscillator
requires close examination of the crystal oscillator temperature sensitivity and frequency drift caused by aging.
Auto Holdover State
The Auto Holdover state is a transitional state that the ZL30410 enters automatically when the active reference fails
unexpectedly. When the ZL30410 detects loss of reference it sets the HOLDOVER status pin and waits in Auto
Holdover state until the failed reference recovers. Recovery from Auto Holdover for 8 kHz, 1.544 MHz, 2.048 MHz
and 19.44 MHz reference clocks is fully automatic, however recovery for an 8 kHz reference clock requires
additional transitioning through the Holdover state to guarantee compliance with network synchronization standards
(for details see section 4.1.3 on page 18 and section 4.1.2 on page 17). The HOLDOVER status may alert the
external control processor (or CPLD logic) about the failure and in response the control processor may switch to the
secondary reference clock. The Auto Holdover and Holdover States are internally combined together and they are
output as a HOLDOVER status on pin 55.
2.4.3 State Transitions
In a typical application, the ZL30410 will most of the time operate in Normal mode (MS2, MS1 == 00) generating
synchronous clocks. Its two Acquisition PLLs will continuously monitor the input references for signs of degraded
quality and output status information for further processing. The status information from the Acquisition PLLs and
the CORE PLL combined with status information from line interfaces and framers (as listed below) forms the basis
for creating reliable network synchronization.
- Acquisition PLLs (PRIOR, SECOR)
- Core PLL (LOCK, HOLDOVER)
- Line interfaces (e.g. LOS - Loss of Signal, AIS - Alarm Indication Signal)
- Framers (e.g. LOF - Loss of frame or Synchronization Status Messages carried over SONET S1 byte or
ESF-DS1 Facility Data Link).
The ZL30410 State Machine is designed to perform some transitions automatically, leaving other less time
dependent tasks to the external controlling processor (or CPLD logic). The state machine includes two stimulus
signals which are critical to automatic operation: “OK --> FAIL” and “FAIL --> OK” that represent loss (and recovery)
of reference signal or its drift by more than ±30000 ppm. Both of them force the Core PLL to transition into and out
of the Auto Holdover state. The ZL30410 State Machine is driven by controlling the mode select pins MS2, MS1 and
RefSel. In order to avoid synchronization problems, the State Machine has built-in basic protection that does not
allow switching the Core PLL into a state where it cannot operate correctly e.g. it is not possible to force the Core
PLL into Normal mode when all references are lost.
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