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參數(shù)資料
| 型號： | ZL30410 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CONN HDR INVERSE 30POS 5ROW VERT |
| 中文描述： | 多業(yè)務線卡鎖相環(huán) |
| 文件頁數(shù)： | 18/38頁 |
| 文件大?。?/td> | 400K |
| 代理商： | ZL30410 |
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ZL30410
Data Sheet
18
Zarlink Semiconductor Inc.
The Core PLL will automatically return to the Normal state after the reference signal recovers from failure. This
transition is shown on the state diagram as a FAIL --> OK change. This change becomes effective when the
reference is restored and there have been no phase hits detected for at least 64 clock cycles for the 1.544/2.048
MHz reference, 512 clock cycles for the 19.44 MHz reference and 1 clock cycle for the 8 kHz reference.
This transition from Auto Holdover to Normal mode is performed as “hit-less” recovery for 1.544 MHz, 2.048 MHz
and 19.44 MHz references. For the 8 kHz input reference, the recovery from Auto Holdover state must transition
through the Holdover state to guarantee “hit-less” recovery (for details see section 4.1.3 on page 18).
4.1.3 Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER -->
NORMAL
The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of the
8 kHz reference. The failure conditions triggering this transition are described in section 4.1.2. When in the Auto
Holdover state, the ZL30410 can return to Normal mode automatically but this transition may exceed Output Phase
Continuity limits specified in the Performance Characteristic Table listed in section “Performance Characteristics”
on page 29. This probable time interval error is avoidable by forcing the PLL into Holdover state immediately after
detection of the 8 kHz reference failure. While in Holdover state the ZL30410 will continue monitoring quality of the
input reference (if a proper ±4.6ppm Master Clock oscillator is employed) and after detecting the presence of a valid
reference it can be switched into Normal state. When the Master Clock Oscillator accuracy exceeds ±4.6ppm range
(leading to inaccurate internal out-of-range detection) then an external method for detecting the presence of the
clock should be employed to switch the ZL30410 into Normal state (0.1 sec after detecting the presence of a valid 8
kHz reference).
Figure 10 - Recovery procedure from a single 8 kHz reference failure by transitioning through
the Holdover state
Ref: OK AND
MS2,MS1=00
{AUTO}
Ref: OK-->FAIL AND
MS2,MS1=00
{AUTO}
MS2,MS1=01 OR
RefSel change
MS2,MS1=10 forces
unconditional return from
any state to Free-run
RESET=1
MS2,MS1=00
OR
MS2,MS1=01
then set MS2,MS1=01
Ref: FAIL-->OK AND
MS2,MS1=00
{AUTO}
RESET
FREE-
RUN
10
HOLD-
OVER
01
NORMAL
00
AUTO
HOLD-
OVER
when HOLDOVER 0-->1
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