參數(shù)資料
型號(hào)： ZL30410
廠商： Zarlink Semiconductor Inc.
英文描述： CONN HDR INVERSE 30POS 5ROW VERT
中文描述： 多業(yè)務(wù)線卡鎖相環(huán)
文件頁(yè)數(shù)： 5/38頁(yè)
文件大小： 400K
代理商： ZL30410
ZL30410
Data Sheet
5
Zarlink Semiconductor Inc.
21
E3DS3/OC3
E3DS3 or OC3 Selection
(Input). In Hardware Control, a logic low on this pin
enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155
clock outputs (high impedance) and sets C34/C44 output to provide C34 and
C44 clocks.
22
E3/DS3
E3 or DS3 Selection
(Input). In Hardware Control, when the E3DS3/OC3 pin
is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44
output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set
low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and
logic high selects 8.592 MHz clock.
23
SEC
Secondary Reference
(Input). This input is used as a secondary reference
source for synchronization. The ZL30410 can synchronize to the falling edge
of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44
MHz clock. In Hardware Control, selection of the input reference is based upon
the RefSel control input. This pin is internally pulled up to VDD.
24
PRI
Primary Reference
(Input). This input is used as a primary reference source
for synchronization. The ZL30410 can synchronize to the falling edge of the 8
kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz
clock. In Hardware Control, selection of the input reference is based upon the
RefSel control input. This pin is internally pulled up to VDD.
25
GND
Ground
.
26
IC
Internal Connection
. Leave unconnected.
27
GND
Ground
.
28
AVDD
Positive Analog Power Supply
. Connect this pin to VDD.
29
VDD
Positive Power Supply
.
30
31
C155N
C155P
Clock 155.52MHz
(LVDS output). Differential outputs for the 155.52 MHz
clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or
they can be disabled by applying logic high. In the disabled state the LVDS
outputs are internally terminated with an integrated 100
resistor (two 50
resistors connected in series). The middle point of these resistors is internally
biased from a 1.25V LVDS bias source.
32
GND
Ground
.
33
NC
No internal bonding Connection.
Leave unconnected.
34
Tdo
IEEE1149.1a Test Data Output
(CMOS output). JTAG serial data is output on
this pin on the falling edge of Tclk clock. If not used, this pin should be left
unconnected.
35
Tms
IEEE1149.1a Test Mode Selection
(3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled up to VDD. If
not used, this pin should be left unconnected.
Pin Description (continued)
Pin #
Name
Description
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