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參數(shù)資料
| 型號： | ZL30410 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CONN HDR INVERSE 30POS 5ROW VERT |
| 中文描述： | 多業(yè)務(wù)線卡鎖相環(huán) |
| 文件頁數(shù)： | 4/38頁 |
| 文件大?。?/td> | 400K |
| 代理商： | ZL30410 |
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ZL30410
Data Sheet
4
Zarlink Semiconductor Inc.
.
Pin Description
Pin #
Name
Description
1
IC
Internal Connection
. Leave unconnected.
2-5
NC
No internal bonding Connection.
Leave unconnected.
6
GND
Ground
. Negative power supply.
7, 8
NC
No internal bonding Connection.
Leave unconnected.
9
FCS
Filter Characteristic Select
(Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30410. Set this pin high to have a loop filter
corner frequency of 6 Hz and limit the phase slope to 41 ns per 1.326 ms. Set
this pin low to have corner frequency of 12 Hz with no phase slope limiting
imposed. This pin is internally pulled down to GND.
10
VDD
Positive Power Supply.
11
GND
Ground
.
12
F16o
Frame Pulse ST-BUS 8.192 Mb/s
(CMOS tristate output). This is an 8 kHz,
61ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s.
13
C16o
Clock 16.384 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
14
C8o
Clock 8.192 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
15
C4o
Clock 4.096 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
16
C2o
Clock 2.048 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
17
F0o
Frame Pulse ST-BUS 2.048 Mb/s
(CMOS tristate output). This is an 8 kHz,
244ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and 4.096
Mb/s.
18
MS1
Mode Select 1
(Input). The MS1 and MS2 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
19
MS2
Mode Select 2
(Input). The MS2 and MS1 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
20
F8o
Frame Pulse ST-BUS/GCI 8.192 Mb/s
(CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192
Mb/s. See Figure 15 for details.
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