參數(shù)資料
型號: ZL30416
廠商: Zarlink Semiconductor Inc.
英文描述: SONET/SDH Clock Multiplier PLL
中文描述: SONET / SDH的時鐘倍頻鎖相環(huán)
文件頁數(shù): 10/22頁
文件大?。?/td> 340K
代理商: ZL30416
ZL30416
Data Sheet
10
Zarlink Semiconductor Inc.
4.2.2 Interfacing to OC-CLKo Output
4.2.2.1 LVPECL to LVPECL Interface
The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and
19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50
termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The
terminating resistors should be placed close to the LVPECL receiver.
Figure 8 - LVPECL to LVPECL Interface
LVPECL
Receiver
LVPECL
Driver
ZL30416
Z=50
Z=50
OC-CLKoP
OC-CLKoN
GND
Typical resistor values: R1 = 127
, R2 =82.5
R1
R2
VCC=+3.3 V
R1
R2
VCC
0.1 uF
+3.3 V
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