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參數(shù)資料
| 型號： | ZL38065QCG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 32 Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 658K |
| 代理商： | ZL38065QCG1 |
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ZL38065
Data Sheet
24
Zarlink Semiconductor Inc.
8.0
Register Description
Power-up
00
hex
ECA: Control Register 1
Page 0
A12=0
A11=0
Bit 2
AdpDis
R/W Address:
00
hex
+ Base Address
Bit 7
Reset
Bit 6
INJDis
Bit 5
BBM
Bit 4
PAD
Bit 3
Bypass
Bit 1
0
Bit 0
ExtDis
Functional Description of Register Bits
When high, the power-up initialization is executed. This presets all register bits including this bit
and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low noise injection is enabled.
Reset
INJDis
BBM
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set
both
BBM bits of the two echo cancellers (Control Register 1) of the same group to
the same logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive
Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on
both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one
128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate
independently.
Bypass
AdpDis
0
ExtDl
Power-up
02
hex
ECB: Control Register 1
Page 0
A12=0
A11=0
Bit 2
AdpDis
R/W Address:
20
hex
+ Base Address
Bit 7
Reset
Bit 6
INJDis
Bit 5
BBM
Bit 4
PAD
Bit 3
Bypass
Bit 1
1
Bit 0
0
Functional Description of Register Bits
When high, the power-up initialization is executed which presets all register bits including this
bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low, noise injection is enabled.
Reset
INJDis
BBM
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set
both
BBM bits of the two echo cancellers (Control Register 1) of the same group to
the same logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive
Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on
both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
Bypass
AdpDis
1
0
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