
ZL38065
Data Sheet
27
Zarlink Semiconductor Inc.
Functional Description of Register Bits
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS
adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the
performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the
echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo
impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby
improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one
tap is equivalent to 125
μ
s (64 ms/512 taps).
FD
7-0
Flat Delay
:
This register defines the flat delay of the MU profile, (i.e., where the MU value is 2
-16
). The
delay is defined as FD
7-0
x 8 taps. For example; If FD
7-0
= 5, then MU=2
-16
for the first 40 taps of the
echo canceller FIR filter. The valid range of FD
7-0
is: 0
≤
FD
7-0
≤
64 in normal mode and 0
≤
FD
7-0
≤
128 in extended-delay mode. The default value of FD
7-0
is zero.
SSC
2-0
Decay Step Size Control
:
This register controls the step size (SS) to be used during the exponential decay
of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter,
where SS = 4 x2
SSC
2-0
. For example; If SSC
2-0
= 4, then MU is reduced by a factor of 2 every 64 taps of
the FIR filter. The default value of SSC
2-0
is 04
hex
.
NS
7-0
Decay Step Number
: This register defines the number of steps to be used for the decay of MU where each
step has a period of SS taps (see SSC
2-0
). The start of the exponential decay is defined as: Filter
Length (512 or 1024) - [Decay Step Number (NS
7-0
) x Step Size (SS)] where SS = 4 x2
SSC
2-0
.
For example; If NS
7-0
=4 and SSC
2-0
=4, then the exponential decay start value is 512 - [NS
7-0
x SS] =
512 - [4 x (4x2
4
)] = 256 taps for a filter length of 512 taps.
Power-up
DB
hex
ECA: Control Register 3
Page 0
A12=0
A11=0
R/W Address:
08
hex
+ Base Address
R/W Address:
28
hex
+ Base Address
Bit 1
PathDet
ECB: Control Register 3
Bit 7
NLRun2
Bit 6
InjCtrl
Bit 5
NLRun1
Bit 4
RingClr
Bit 3
Reserve
Bit 2
PathClr
Bit 0
NMatcj
Functional Description of Register Bits
Reserved
Reserved
NLRun1
Reserved bit.
Reserved bit.
When high, the comfort noise level estimator actively rejects uncancelled echo as being
background noise. When low, the noise level estimator makes no such distinction.
RingClr
When high, the instability detector is activated. When low, the instability detector is disabled.
Reserved bit. Must always be set to one for normal operation.
When high, the current echo channel estimate will be cleared and the echo canceller will enter
fast convergence mode upon detection of a path change. When low, the echo canceller will
keep the current path estimate but revert to fast convergence mode upon detection of a path
change. Note: this bit is ignored if PathDet is low.
When high, the path change detector is activated. When low, the path change detector is
disabled.
Reserved bit.
Reserve
PathClr
PathDet
Reserved