參數(shù)資料
型號： ZL38065QCG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： 32 Channel Voice Echo Canceller
中文描述： DATACOM, ISDN ECHO CANCELLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BED, LQFP-100
文件頁數(shù)： 33/48頁
文件大?。?/td> 658K
代理商： ZL38065QCG1
ZL38065
Data Sheet
33
Zarlink Semiconductor Inc.
Power-up
08
hex
ECA: Low Power Threshold (LPTHRES)
Page 0
A12=0
A11=0
R/W Address:
1F
hex
+ Base Address
R/W Address:
3F
hex
+ Base Address
Bit 1
LPTH1
ECB: Low Power Threshold (LPTHRES)
Bit 7
LPTH7
Bit 6
LPTH6
Bit 5
LPTH5
Bit 4
LPTH4
Bit 3
LPTH3
Bit 2
LPTH2
Bit 0
LPTH0
Functional Description of Register Bits
This register is used to control the RIN low power threshold. The threshold is set by LPTHRES << 4 and is
compared to RIN. Raising LPTHRES makes the VEC less responsive to very small signals.
Power-up
N/A
ECA: Estimated Echo Cancellation Level 2 (SUP)
Page 1
A12=0
A11=1
R/W Address:
05
hex
+ Base Address
R/W Address:
25
hex
+ Base Address
Bit 1
SUP9
ECB: Estimated Echo Cancellation Level 2 (SUP)
Bit 7
SUP15
Bit 6
SUP14
Bit 5
SUP13
Bit 4
SUP12
Bit 3
SUP11
Bit 2
SUP10
Bit 0
SUP8
Power-up
N/A
ECA: Estimated Echo Cancellation Level 1 (SUP)
Page 1
A12=0
A11=1
Read Address:
04
hex
+ Base Address
Read Address:
24
hex
+ Base Address
Bit 1
SUP1
ECB: Estimated Echo Cancellation Level 1 (SUP)
Bit 6
Bit 5
SUP6
SUP5
Functional Description of Register Bits
This register is the estimate of the level of error as compared to RUN. SUP is used to detect low-level
double-talk and to select convergence speed (fast or slow). This register is a 16 bit 2’s complement linear
value and defaults to 4800
hex
= 0 dB. As cancellation progresses, this value decreases with its lower limit
set by ERLLOW. It is reset after a path change or reset/bypass operation.
Bit 7
SUP7
Bit 4
SUP4
Bit 3
SUP3
Bit 2
SUP2
Bit 0
SUP0
Power-up
N/A
ECA: Residual Error Signal 2 (ERR)
Page 1
A12=0
A11=1
Read Address:
07
hex
+ Base Address
Read Address:
27
hex
+ Base Address
Bit 1
ERR9
ECB: Residual Error Signal 2 (ERR)
Bit 7
ERR15
Bit 6
ERR14
Bit 5
ERR13
Bit 4
ERR12
Bit 3
ERR11
Bit 2
ERR10
Bit 0
ERR8
Power-up
N/A
ECA: Residual Error Signal 1 (ERR)
Page 1
A12=0
A11=1
Read Address:
06
hex
+ Base Address
Read Address:
26
hex
+ Base Address
Bit 1
ERR1
ECB: Residual Error Signal 1 (ERR)
Bit 5
ERR5
Functional Description of Register Bits
This register represents the error signal after the filter and prior to NLP. This register is a 16 bit 2’s
complement linear value.
Bit 7
ERR7
Bit 6
ERR6
Bit 4
ERR4
Bit 3
ERR3
Bit 2
ERR2
Bit 0
ERR0
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