參數(shù)資料
型號: ZL38065QCG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: 32 Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BED, LQFP-100
文件頁數(shù): 31/48頁
文件大?。?/td> 658K
代理商: ZL38065QCG1
ZL38065
Data Sheet
31
Zarlink Semiconductor Inc.
Power-up
0C
hex
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
Page 0
A12=0
A11=0
R/W Address:
19
hex
+ Base Address
R/W Address:
39
hex
+ Base Address
Bit 1
NLP9
ECB: Non-Linear Processor Threshold Register 2
(NLPTHR)
Bit 6
Bit 5
NLP14
NLP13
Bit 7
NLP15
Bit 4
NLP12
Bit 3
NLP11
Bit 2
NLP10
Bit 0
NLP8
Power-up
E0
hex
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
Page 0
A12=0
A11=0
R/W Address:
18
hex
+ Base Address
ECB: Non-Linear Processor Threshold Register 1
(NLPTHR)
Bit 6
Bit 5
NLP6
NLP5
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16
bit 2’s complement linear value defaults to 0CE0
hex
= 0.1 or -20.0 dB. The maximum value is 7FFF
hex
=
0.9999 or 0 dB.
R/W Address:
38
hex
+ Base Address
Bit 7
NLP7
Bit 4
NLP4
Bit 3
NLP3
Bit 2
NLP2
Bit 1
NLP1
Bit 0
NLP0
Power-up
40
hex
ECA: Adaptation Step Size Register 2 (MU)
Page 0
A12=0
A11=0
R/W Address:
1B
hex
+ Base Address
R/W Address:
3B
hex
+ Base Address
Bit 1
MU9
ECB: Adaptation Step Size Register 2 (MU)
Bit 7
MU15
Bit 6
MU14
Bit 5
MU13
Bit 4
MU12
Bit 3
MU11
Bit 2
MU10
Bit 0
MU8
Power-up
00
hex
ECA: Adaptation Step Size Register 1 (MU)
Page 0
A12=0
A11=0
R/W Address:
1A
hex
+ Base Address
R/W Address:
3A
hex
+ Base Address
Bit 1
MU1
ECB: Adaptation Step Size Register 1 (MU)
Bit 6
Bit 5
MU6
MU5
Functional Description of Register Bits
This register allows the user to program the level of MU, which is the LMS filter step size. Increasing this
value can speed up convergence times, but can also potentially decrease VEC stability. MU is a 16 bit 2’s
complement value which defaults to 4000
hex
= 1.0 The maximum value is 7FFF
hex
or 1.9999 decimal. The
high byte is in Register 2 and the low byte is in Register 1.
Bit 7
MU7
Bit 4
MU4
Bit 3
MU3
Bit 2
MU2
Bit 0
MU0
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