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參數(shù)資料
| 型號： | ZL50030 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機的H.110接口和1畝× 1畝本地交換 |
| 文件頁數(shù)： | 16/73頁 |
| 文件大?。?/td> | 681K |
| 代理商： | ZL50030 |
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ZL50030
Data Sheet
16
Zarlink Semiconductor Inc.
5.0 Local Input Delay Selection
The local input delay selection allows individual local input streams to be aligned and shifted against the input frame
pulse (FRAME_A_io or FRAME_B_io). This feature compensates for the variable path delays in the local interface.
Such delays can occur in large centralized and distributed switching systems.
Each local input stream can have its own bit delay offset value by programming the local input bit delay selection
registers (LIDR0 to LIDR5). See Table 11, "Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits" on page 39, for
the contents of these registers. Possible bit adjustment can range up to +7
3/4
bit periods forward with resolution of
1/4
bit period. See Table 12 on page 39 and Figure 12 on page 40 for local input delay programming.
6.0 Output Advancement Selection
The ZL50030 allows users to advance individual backplane or local output streams with respect to the frame
boundary. This feature is useful in compensating for variable output delays caused by various output loading
conditions. Each output stream can have its own advancement value programmed by the output advancement
registers. The backplane output advancement registers (BOAR0 to BOAR3) are used to program the backplane
output advancement. The local output advancement registers (LOAR0 to LOAR1) are used to program the local
output advancement. Possible adjustment for local and backplane output data streams is 22.5 ns with a resolution
of 7.5 ns. The advancement is independent of the output data rate. Table 13 on page 41 and Figure 13, "Example
of Backplane Output Advancement Timing" on page 41, and Table 14 on page 42 and Figure 14, "Local Output
Advancement Timing" on page 42 describe the details of the output advancement programming for the backplane
and local interfaces respectively.
7.0 Local Output Timing Considerations
The output data of the ZL50030’s local side is slightly advanced with respect to the frame and bit boundary as
defined by the local output clocks and frame pulses (ST_FPo0, ST_CKo0, ST_FPo1, ST_CKo1). The advancement
is in the range of 5 ns to 17 ns. Despite this advancement, the ZL50030 will operate within the parameters specified
in the datasheet because input data are usually sampled at the 3/4 or 1/2 point of the bit cell. However, the user
should be cautious when introducing additional delay to the clock signals only (e.g., by passing them through glue
logic, FPGA, or CPLD), which will introduce a few nanoseconds of delay relative to the data. If the clock signal is
delayed, data will be advanced from the receiver device’s point of view. This may cause errors in sampling the data.
Using an example where a 3/4 sampling point is used, there is about 30 ns from the sampling point to the end of the
bit cell. With a worst-case of 17 ns advancement, the timing margin will be approximately 13 ns. Any additional
delays applied to the local output clocks (ST_CKo0 and ST_CKo1) must not exceed 13 ns minus the hold time of
the receiving device. Delays applied to both clocks and data equally will not impact the device operation.
8.0 Memory Block Programming
The ZL50030 block programming mode (BPM) register provides users with the capability of initializing the local and
backplane connection memories in two frames. Bit 13 - bit 15 of every backplane connection memory location will
be programmed with the pattern stored in bit 6 - bit 8 of the BPM register. Bit 13 - bit 15 of every local connection
memory location will be programmed with the pattern stored in bits 3 to 5 of the BPM register. The other bit
positions of the backplane connection memory and the local connection memory are loaded with zeros. See Figure
4 on page 17 for the connection memory contents when the device is in block programming mode.
The block programming mode is enabled by setting the memory block program (MBP) bit of the Control Register to
high. After the block programming enable (BPE) bit of the BPM register is set to high, the block programming data
will be loaded into bits 13 to 15 of every backplane connection memory location and bits 13 to 15 of every local
connection memory location. The other connection memory bits are loaded with zeros. When the memory block
programming is completed, the device resets the BPE bit to low. See Table 10 on page 37 for the bit assignment of
the BPM register.
相關(guān)PDF資料 |
PDF描述 |
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| ZL50030GAC | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
| ZL50031 | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50031QEG1 | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50053QCC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50030_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch |
| ZL50030GAC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays |
| ZL50030GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW |
| ZL50031 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50031QEG1 | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP |
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