參數(shù)資料
型號(hào): ZL50030
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述: 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和1畝× 1畝本地交換
文件頁數(shù): 69/73頁
文件大?。?/td> 681K
代理商: ZL50030
ZL50030
Data Sheet
69
Zarlink Semiconductor Inc.
Figure 35 - Serial Output and External Control
Figure 36 - Output Driver Enable (ODE)
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
*Note 1: A delay of 100 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high.
*Note 2: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel the time taken to discharge C
L
.
AC Electrical Characteristics
- Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
1
CS setup from DS falling
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
DDR
t
DHR
0
ns
2
R/W setup from DS falling
15
ns
3
Address setup from DS falling
5
ns
4
CS hold after DS rising
0
ns
5
R/W hold after DS rising
0
ns
6
Address hold after DS rising
5
ns
7
Data setup from DTA Low on Read
20
ns
C
L
= 30 pF
8
Data hold on read
20
ns
C
L
= 30 pF,
R
L
= 1 K
See Note 2
9
Valid Write Data Setup
t
WDS
t
DHW
t
AKD
20
ns
10
Data hold on write
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
8
ns
11
97/82
158/114
110/95
171/127
30
ns
ns
C
L
=30pF
C
L
=30pF
C
L
=30pF, R
L
=1K,
See Note 2
12
Acknowledgment Hold Time
t
AKH
ns
t
DZ
LSTio/BSTio
(Output)
t
ZD
LSTio/BSTio
(Output)
C8_A_io
C8_B_io
V
TT
V
TT
Tri-state
Valid Data
V
TT
Tri-state
Valid Data
(Input)
V
TT
HiZ
HiZ
LSTio/BSTio
(Output)
ODE
t
ZD_ODE
Valid Data
V
TT
t
DZ_ODE
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