參數(shù)資料
型號(hào)： ZL50030
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和1畝× 1畝本地交換
文件頁數(shù)： 30/73頁
文件大?。?/td> 681K
代理商： ZL50030
ZL50030
Data Sheet
30
Zarlink Semiconductor Inc.
When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the
output frame boundary, always keeping the described relation to the CT_C8 clock.
When the reference frequency is 8.192 MHz, the output frame pulse (CT_FRAME) has to be aligned with the
input frame pulse (FRAME_A_io or FRAME_B_io). Since an 8.192 MHz clock (either C8_A_io or C8_B_io)
is used as the reference clock, the selected frame pulse from the Frame Select MUX is provided as the input
to the Divider circuit and the CT_FRAME is synchronized to it.
17.9 Frequency Select MUX Circuit
According to the selected input reference of the DPLL, this MUX will select the appropriate output frequency to be
the feedback signal to the PLL and MTIE Circuits.
18.0 Measures of DPLL Performance
The following are some the DPLL performance indicators and their corresponding definitions.
18.1 Intrinsic Output Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as freerun or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the
applicable standards. See “AC Electrical Characteristics- Output Clock Jitter Generation (Unfiltered)” on page 64
for jitter values.
18.2 Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depend on the applicable standards. The input jitter
tolerance of the DPLL depends on the selected reference frequency and can not exceed:
±
15 U.I. for E1 or T1
references, and
±
1 U.I. for 8 kHz references.
18.3 Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
In slave and secondary master mode the H.110 standard requires the “B Clocks” to be edge-synchronous with the
“A Clocks”, as long as jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications. Therefore in these
two modes no jitter attenuation is performed.
In primary master mode the jitter attenuation of the DPLL is determined by the internal 1.52Hz low pass Loop Filter
and the Phase Slope Limiter. Figure 10, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on
page 31 shows the DPLL jitter transfer function diagram in a wide range of frequencies, while Figure 11, "Detailed
DPLL Jitter Transfer Function Diagram" on page 32 is the portion of the diagram from Figure 10 around 0dB of the
jitter transfer amplitude. At this point it is possible to see that when operating in primary master mode the DPLL is a
second order, type 2 PLL. The jitter transfer function can be described as a low pass filter to 1.52Hz, -20dB/decade,
with peaking less then 0.5dB.
All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Since 1 U.I. at
1.544 MHz (648 ns
PP
) is not equal to 1 U.I. at 2.048 MHz (488 ns
PP
). a transfer value using different input and
output frequencies must be calculated in common units (e.g. seconds) as shown in the following example:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50030_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
ZL50030GAC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays
ZL50030GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW
ZL50031 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
ZL50031QEG1 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP
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