參數(shù)資料
型號(hào)： ZL50030
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
中文描述： 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和1畝× 1畝本地交換
文件頁(yè)數(shù)： 21/73頁(yè)
文件大?。?/td> 681K
代理商： ZL50030
ZL50030
Data Sheet
21
Zarlink Semiconductor Inc.
In the switching mode, the contents of the local connection memory stream address bits (LSAB4-0) and the channel
address bits (LCAB7-0) define the source information (stream and channel) of the time slot that will be switched to
the local LSTio streams. During message mode, only the 8 least significant bits of the local connection memory bits
are transferred to the LSTio pins.
14.0 Bit Error Rate Test
The ZL50030 offers users a Bit Error Rate (BER) test feature for the backplane and the local interfaces. The
circuitry of the BER test consists of a transmitter and a receiver on both interfaces that can transmit and receive the
BER patterns independently. The transmitter can output a pseudo-random pattern of the form 2
15
- 1 to any channel
and any stream within a frame. For the test, users can program the output channel and stream through the
backplane or local connection memory and the input channel and stream using Local or Backplane BER Input
Selection (BIS) registers. See Table 15 on page 43 and Table 17 on page 43 for the LBIS and the BBIS registers
contents, respectively.
The receiver receives the BER pattern and does an internal BER pattern comparison. For backplane interface, the
comparison result is stored in the Backplane BER register (BBERR). For local interface, the result is stored in the
Local BER register (LBERR).
15.0 DPLL
The Digital Phase Locked Loop (DPLL) accepts selectable 2.048 MHz, 1.544 MHz or 8 kHz input reference signals.
It accepts reference inputs from independent sources and provides bit-error-free reference switching. The DPLL
meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard.
The DPLL also provides the timing for the rest of the ZL50030 Digital Switch, generating several network clocks
with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the
requirements of the H.110 clock specification.
15.1 ZL50030 Modes of Operation
The DPLL, and consequently the ZL50030, can, as required by the H.110 standard, operate in three different
modes: Primary Master, Secondary Master and Slave. See Figure 5, "Typical Timing Control Configuration" on
page 22.
To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 19 on page 44 and
Table 20 on page 47 for the contents of these registers.
In all modes the ZL50030 monitors both the “A Clocks” (C8_A_io and FRAME_A_io) and the “B Clocks” (C8_B_io
and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the “A Clocks” and “B Clocks”
respectively.
相關(guān)PDF資料
PDF描述
ZL50030GAC Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50030_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 1 K x 1 K Local Switch
ZL50030GAC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays
ZL50030GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 2K/1K X 1K 3.3V/5V 220BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE FLEX 4KX2K DX+H.110 I/FACE+1K SW
ZL50031 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
ZL50031QEG1 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP
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