– xiv –
LIST OF TABLES (2/3)
Table No.
Title
Page
9-1.
9-2.
9-3.
9-4.
9-5.
Watchdog Timer Inadvertent Detection Time.......................................................................
Interval Time .........................................................................................................................
Watchdog Timer Configuration.............................................................................................
Watchdog Timer Overrun Detection Time............................................................................
Interval Timer Interval Time..................................................................................................
155
155
156
161
162
10-1.
6-Bit Up/Down Counter Configuration ..................................................................................
163
11-1.
Clock Output Control Circuit Configuration ..........................................................................
168
12-1.
Buzzer Output Control Circuit Configuration ........................................................................
171
13-1.
A/D Converter Configuration ................................................................................................
175
14-1.
14-2.
14-3.
14-4.
Differences between Channels 0 and 1 ...............................................................................
Difference of Serial Interface Channel 0 Mode ....................................................................
Serial Interface Channel 0 Configuration .............................................................................
Various Signals in SBI Mode ................................................................................................
189
190
191
219
15-1.
15-2.
15-3.
15-4.
Difference of Serial Interface Channel 1 Mode ....................................................................
Serial Interface Channel 1 Configuration .............................................................................
Interval Time by CPU Processing (During Internal Clock Operation)..................................
Interval Time by CPU Processing (During External Clock Operation) ................................
235
236
275
276
16-1.
16-2.
Relation between Display Output Pins and Port Pins ..........................................................
FIP Controller/Driver Configuration ......................................................................................
279
279
17-1.
17-2.
17-3.
17-4.
Interrupt Source List .............................................................................................................
Various Flags Corresponding to Interrupt Request Sources ...............................................
Times from Maskable Interrupt Request Generation to Interrupt Service ...........................
Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ........................
296
299
310
314
18-1.
18-2.
18-3.
18-4.
HALT Mode Operating Status ..............................................................................................
Operation after HALT Mode Release ...................................................................................
STOP Mode Operating Status..............................................................................................
Operation after STOP Mode Release ..................................................................................
323
325
326
328
19-1.
Hardware Status after Reset ................................................................................................
331
20-1.
20-2.
20-3.
20-4.
Difference between
μ
PD78P048A and Mask ROM Versions ..............................................
Memory Size Switching Register Value at Reset.................................................................
IXS Register Settings............................................................................................................
PROM Programming Operating Modes ...............................................................................
333
334
335
336