CHAPTER 14 SERIAL INTERFACE CHANNEL 0
227
(9) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following
two conditions are satisfied.
Serial interface channel 0 operation control bit (CSIE0)= 1
Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1.
If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
Because the N-ch open-drain output must be made to go into a high-impedance state
during data reception, write FFH to SIO0 in advance. However, when make-up function
specify bit (WUP) = 1, the N-ch open-drain output always goes into a high-impedance
state. Thus, it is not necessary to write FFH to SIO0.
If data is written to SIO0 when the slave is busy, the data is not lost.
When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY)
state, transfer starts.
2.
3.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
For pin (SB0 or SB1) which is to be used for data input/output, be sure to carry out the following settings
before serial transfer of the 1st byte after RESET input.
[1] Set the P25 and P26 output latches to 1.
[2] Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
[3] Reset the P25 and P26 output latches from 1 to 0.
(10) Judging busy status of slave
When device is in the master mode, follow the procedure below to judge whether slave device is in the busy
state or not.
[1] Detect acknowledge signal (ACK) or interrupt request signal generation.
[2] Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode.
[3] Read out the pin state (when the pin level is high, the READY state is set).
After the detection of the READY state, set the port mode register to 0 and return to the output mode.
(11) SBI mode precautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, match interrupt (CSIIF0) of the address to be generated with WUP = 1 is
normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) If WUP is set to 1 during BUSY signal output, BUSY is not cleared. In SBI, the BUSY signal continues
to be output after BUSY clear instruction generation to the falling edge of the next serial clock (SCK0).
Before setting WUP to 1, be sure to clear BUSY and then check that the SB0 (SB1) has become high-
level.