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CHAPTER 12 WATCHDOG TIMER FUNCTION
12.4 Cautions
12.4.1 General cautions on use of watchdog timer
(1) The watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program
loops. Therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog
timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing
to be performed that will restore the normal state or establish a stable state and then stop the operation.
(2) The watchdog timer cannot detect inadvertent program loops in the following cases.
<1>
<2>
<3>
If watchdog timer clearance is performed in the timer interrupt processing program
If cases where an interrupt request or macro service is held pending (refer to
16.9
) occur consecutively
If the watchdog timer is cleared periodically when the program is looping inadvertently due to an error in the
program logic (if each module of the program functions normally but the overall program does not)
If the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program
loop occurs
If the STOP mode, HALT mode, or IDLE mode is entered as the result of an inadvertent program loop
If an inadvertent program loop of watchdog timer also occurs in the event of CPU hang up due to external noise
<4>
<5>
<6>
In cases <1>, <2> and <3> the program can be amended to allow detection to be performed.
In case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. Similarly, in case <5>, the
STOP mode, HALT mode, or IDLE mode cannot be set unless a 4-byte dedicated instruction is used. For state <2>
to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a
specific pattern (e.g. BT PSWL. bit, $$, etc.). Therefore, the establishment of state <2> as the result of <4>, <5>
or an inadvertent program loop is likely to be extremely rare.