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CHAPTER 3 CPU ARCHITECTURE
3.10 Cautions
(1) Program fetches cannot be performed from the internal high-speed RAM area (0FD00H to 0FEFFH when the
LOCATION 0 instruction is executed; FFD00H to FFEFFH when the LOCATION 0FH instruction is executed).
(2) Special function registers (SFRs)
Addresses onto which SFRs are not assigned should not be accessed in the area 0FF00H to 0FFFFH
Note
. If such
an address is accessed by mistake, the
m
PD784046 may become deadlocked. A deadlock can only be released
by reset input.
Note
When the LOCATION 0 instruction is executed; FFF00H to FFFFFH when the LOCATION 0FH instruction
is executed.
(3) Writing to the internal memory size select register (IMS) is valid only with the
m
PD78F4046. The IMS of the
m
PD784044 and 784046 holds the value at RESET even if data is written to it.
(4) To develop a program for the
m
PD784044 using the
m
PD78F4046, set the value of the IMS to CDH. When the value
of the IMS is set to CDH, the peripheral RAM capacity of the
m
PD78F4046 is 768 bytes, but the peripheral RAM
capacity of the
m
PD784044 is 512 bytes. When using a mask ROM, therefore, exercise care that addresses 0FA00H
through 0FAFFH of the peripheral RAM area of the
m
PD78F4046 are not used (when the LOCATION 0 instruction
is executed).
(5) Stack pointer (SP) operation
With stack addressing, the entire 1 M-byte space can be accessed, but a stack area cannot be reserved in the SFR
area or internal ROM area.
(6) Stack pointer (SP) initialization
The SP is undefined after RESET input, while non-maskable interrupts can be acknowledged directly after reset
release. Therefore, an unforeseen operation may be performed if a non-maskable interrupt request is generated
while the SP is in the undefined state directly after reset release. To minimize this risk, the following program should
be coded without fail after reset release.
RSTVCT
CSEG
DW
to
CSEG
LOCATION 0H ; or LOCATION 0FH
MOVG SP, #STKBGN
AT
RSTSTRT
0
INITSEG
RSTSTRT :
BASE