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CHAPTER 16 INTERRUPT FUNCTIONS
Table 16-4. Interrupt Control Register Flags Corresponding to Interrupt Sources (2/2)
Default
Priority
Interrupt
Request
Signal
Interrupt Control Registers
Interrupt
Request Flag
Interrupt
Mask Flag
Macro Service
Enable Flag
Context Switching
Enable Flag
Priority Speci-
fication Flag
20
INTST
STIC
STIF
STMK
STISM
STCSE
STPR0
STPR1
21
INTSER2
SERIC2
SERIF2
SERMK2
SERISM2
SERCSE2
SERPR20
SERPR21
22
INTSR2
SRIC2
SRIF2
SRMK2
SRISM2
SRCSE2
SRPR20
SRPR21
INTCSI2
CSIIC2
CSIIF2
CSIMK2
CSIISM2
CSICSE2
CSIPR20
CSIPR21
23
INTST2
STIC2
STIF2
STMK2
STISM2
STCSE2
STPR20
STPR21
24 (lowest)
INTAD
ADIC
ADIF
ADMK
ADISM
ADCSE
ADPR0
ADPR1
16.3.1 Interrupt control registers
An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for
the corresponding interrupt request. The interrupt control register format is shown in Figure 16-1.
(1) Priority specification flags (
¥¥
PR1,
¥¥
PR0)
The priority specification flags specify the priority on an individual interrupt source basis for the 25 maskable
interrupts.
Up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. Among
maskable interrupt sources, level 0 is the highest priority.
If multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they
are acknowledged in default priority order.
These flags can be manipulated bit-wise by software.
RESET input sets all bits to “1”.
(2) Context switching enable flag (
¥¥
CSE)
The context switching enable flag specifies that a maskable interrupt request is to be processed by context switching.
In context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector
address stored beforehand in the register bank, and at the same time the current contents of the program counter
(PC) and program status word (PSW) are saved in the register bank.
Context switching is suitable for real-time processing, since execution of interrupt processing can be started faster
than with normal vectored interrupt processing.
This flag can be manipulated bit-wise by software.
RESET input sets all bits to “0”.