400
CHAPTER 16 INTERRUPT FUNCTIONS
16.7.3 Maskable interrupt priority levels
The
m
PD784046 performs multiple interrupt processing in which an interrupt is acknowledged during processing of
another interrupt. Multiple interrupts can be controlled by priority levels.
There are two kinds of priority control, control by default priority and programmable priority control in accordance with
the setting of the priority specification flag. In priority control by means of default priority, interrupt service is performed in
accordance with the priority preassigned to each interrupt request (default priority) (refer to
Table 16-2
). In programmable
priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. Interrupt
requests for which multiple interruption is permitted are shown in Table 16-5.
Since the IE flag is cleared (0) automatically when an interrupt is acknowledged, when multiple interruption is used, the
IE flag should be set (1) to enable interrupts by executing an EI instruction in the interrupt processing program, etc.
Table 16-5. Multiple Interrupt Processing
Priority of Interrupt Currently
Being Acknowledged
ISPR Value
IE Flag in PSW
PRSL in
IMC Register
Acknowledgeable Maskable Interrupts
No interrupt being
00000000
0
¥
All macro service only
acknowledged
1
¥
All maskable interrupts
3
00001000
0
¥
All macro service only
1
0
All maskable interrupts
1
1
All macro service
Maskable interrupts specified as
priority 0/1/2
2
0000
¥
100
0
¥
All macro service only
1
¥
All macro service
Maskable interrupts specified as
priority 0/1
1
0000
¥¥
10
0
¥
All macro service only
1
¥
All macro service
Maskable interrupts specified as
priority 0
0
0000
¥¥¥
1
¥
¥
All macro service only
Non-maskable interrupts
1000
¥¥¥¥
0100
¥¥¥¥
1100
¥¥¥¥
¥
¥
All macro service only
Remark
¥
: don’t care