– ii –
CHAPTER 3 CPU ARCHITECTURE .................................................................................................
33
3.1
Memory Spaces...............................................................................................................
3.1.1
Internal program memory space .......................................................................................
3.1.2
Internal data memory space ..............................................................................................
3.1.3
Special Function Register (SFR) area ..............................................................................
3.1.4
Data memory addressing...................................................................................................
Processor Registers.......................................................................................................
3.2.1
Control registers.................................................................................................................
3.2.2
General registers................................................................................................................
3.2.3
Special Function Register (SFR).......................................................................................
Instruction Address Addressing ..................................................................................
3.3.1
Relative Addressing ...........................................................................................................
3.3.2
Immediate addressing........................................................................................................
3.3.3
Table indirect addressing...................................................................................................
3.3.4
Register addressing ...........................................................................................................
Operand Address Addressing ......................................................................................
3.4.1
Implied addressing .............................................................................................................
3.4.2
Register addressing ...........................................................................................................
3.4.3
Direct addressing ...............................................................................................................
3.4.4
Short direct addressing......................................................................................................
3.4.5
Special-Function Register (SFR) addressing ...................................................................
3.4.6
Register indirect addressing ..............................................................................................
3.4.7
Based addressing ..............................................................................................................
3.4.8
Based indexed addressing ................................................................................................
3.4.9
Stack addressing................................................................................................................
33
35
36
36
37
39
39
41
43
46
46
47
48
48
49
49
50
51
52
53
54
55
56
56
3.2
3.3
3.4
CHAPTER 4 PORT FUNCTIONS ......................................................................................................
57
4.1
4.2
Port Functions.................................................................................................................
Port Configuration ..........................................................................................................
4.2.1
Port 0 ..................................................................................................................................
4.2.2
Port 1 ..................................................................................................................................
4.2.3
Port 2 ..................................................................................................................................
4.2.4
Port 3 ..................................................................................................................................
4.2.5
Port 7 ..................................................................................................................................
4.2.6
Port 8 ..................................................................................................................................
4.2.7
Port 9 ..................................................................................................................................
4.2.8
Port 10 ................................................................................................................................
4.2.9
Port 11 ................................................................................................................................
Port Function Control Registers ..................................................................................
Port Function Operations ..............................................................................................
4.4.1
Writing to input/output port ................................................................................................
4.4.2
Reading from input/output port..........................................................................................
4.4.3
Operations on input/output port.........................................................................................
57
60
60
62
63
65
66
68
69
70
71
72
77
77
77
77
4.3
4.4