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參數(shù)資料
| 型號(hào)： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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18
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 9: Crystal Loop Tuning Bits
Name
Description
XLCP[1:0]
(Bits 53-52)
Crystal Loop Charge Pump Current
Bit 53 = 0
Bit 52 = 0
Current = 1.5
mA
Bit 53 = 0
Bit 52 = 1
Current = 5
mA
Bit 53 = 1
Bit 52 = 0
Current = 8
mA
Bit 53 = 1
Bit 52 = 1
Current = 24
mA
XLROM[2:0]
(Bits 51-49)
Crystal Loop Diivder ROM Select and Crystal Oscillator Power-Down
(see Table 10)
XLVTEN
(Bit 61)
Crystal Loop Voltage Fine Tune ENable
Bit = 0
Disabled (fine tune is inactive)
Bit = 1
Enabled (fine tune is active)
XLSWAP
(Bit 54)
Crystal Loop SWAP Polarity
Bit = 0
Use with an external VCXO that
increases in frequency in response to
an increasing voltage at the XTUNE
pin.
Bit = 1
Use with a VCXO that increases in
frequency in response to a
decreasing voltage at the XTUNE pin.
Use this setting for internal VCXO
XLPDEN
(Bit 55)
Crystal Loop Power Down Enable
Bit = 0
Disabled (crystal loop operates)
Bit = 1
Enabled
(crystal loop is powered down)
XCT[3:0]
(Bits 59-56)
Crystal Coarse Tune (see Table 11)
Table 10: Crystal Loop Control ROM
XLROM[2]
XLROM[1]
XLROM[0]
VCXO Divider
Crystal Frequency (MHz)
0
1
-
0
1
3072
24.576
0
1
0
3156
25.248
0
1
2430
19.44
1
0
2500
20.00
1
0
1
4000
32.00
1
0
3375
27.00
1
Crystal oscillator power-down
6.1 VCXO Coarse Tune
The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via XCT[3:0]. The actual amount of frequency
warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load
capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of the VCXO can be enabled
by setting the XLVTEN bit to a logic-one, or disabled by setting the bit to a logic-zero.
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