參數(shù)資料
型號: 11274-502-XTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16
封裝: 0.150 INCH, GREEN, SOIC-16
文件頁數(shù): 13/40頁
文件大?。?/td> 746K
代理商: 11274-502-XTD
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 14: DC Electrical Specifications
20
AMI Semiconductor
www.amis.com
Parameter
Symbol
Conditions/Description
Min.
Typ.
Max.
Units
Overall
Supply current, dynamic, (with loaded outputs)
IDD
fCLK = 66MHz; CMOS mode, VDD = 5.5V
100
mA
Supply current, static
IDDL
SHUT = 1, XLROM[2:0] = 7, XLPDEN = 1,
VDD = 5.5V
12
mA
Serial Communication I/O (SDA, SCL)
High-level input voltage
VIH
Outputs off
3.5
VDD+0.3
V
Low-level input voltage
VIL
Outputs off
VSS-0.3
1.5
V
Hysteresis voltage*
Vhys
Outputs off
2
V
Input leakage current
II
-1
1
mA
Low-level output sink current (SDA)
IOL
VOL = 0.4V
20
32
mA
Tristate output current
IZ
-10
10
mA
Address Select Input (ADDR)
High-level input voltage
VIH
2.4
VDD+0.3
V
Low-level input voltage
VIL
VSS-0.3
0.8
V
High-level input current (pull-down)
IIH
VIH = VDD = 5.5V
5
16
30
mA
Low-level input current
IIL
-2
2
mA
Reference Frequency Input (REF, FBK)
High-level input voltage
VIH
3.5
VDD+0.3
V
Low-level input voltage
VIL
VSS-0.3
1.5
V
Hysteresis voltage
Vhys
500
mV
Input leakage current
II
-1
1
mA
Loop Filter Input (EXTLF)
Input leakage current
II
EXTLF = 0
-1
1
mA
High-level output source current
IOH
V0 = 0.8V; EXTLF = 1, MLCP[1:0] = 0
-1.5
mA
V0 = 0.8V; EXTLF = 1, MLCP[1:0] = 1
-5
V0 = 0.8V; EXTLF = 1, MLCP[1:0] = 2
-8
V0 = 0.8V; EXTLF = 1, MLCP[1:0] = 3
-24
Low-level output sink current
IOL
V0 = 4.2V; EXTLF = 1, MLCP[1:0] = 0
1.5
mA
V0 = 4.2V; EXTLF = 1, MLCP[1:0] = 1
5
V0 = 4.2V; EXTLF = 1, MLCP[1:0] = 2
8
V0 = 4.2V; EXTLF = 1, MLCP[1:0] = 3
25
Crystal Oscillator Input (XIN)
Threshold bias voltage
VTH
1.5
2.2
3.5
V
High-level input current
IIH
Outputs off; VIH = 5V
10
24
30
mA
Low-level input current
IIL
Outputs off; VIL = 0V
-10
-19
-30
mA
Crystal loading capacitance*
CL(xtal)
As seen by an external crystal connected to XIN
and XOUT; VCXO tuning disabled
10
pF
Input loading capacitance*
CL(XIN)
As seen by an external clock driver on XOUT;
XIN unconnected, VCXO disabled
20
pF
Crystal Oscillator Output (XOUT)
High-level output source current
IOH
V0 = 0V, float XIN
-20
-30
-50
mA
Low-level output sink current
IOL
V0 = 5V, float XIN
-20
-40
-50
mA
VCXO Tuning I/O (XTUNE)
High-level input voltage
VIH
Lock status: out-of-range HIGH
3.2
VDD+0.3
V
Low-level input voltage
VIL
Lock status: out-of-range LOW
VSS-0.3
0.3
V
Hysteresis voltage
Vhys
1.0
V
Input leakage current
II
XLPDEN = 0
-1
1
mA
High-level output source current
IOH
V0 = 0.8V; XLDP[1:0] = 0
-1.5
mA
V0 = 0.8V; XLDP[1:0] = 1
-5
V0 = 0.8V; XLDP[1:0] = 2
-8
V0 = 0.8V; XLDP[1:0] = 3
-24
Low-level output sink current
IOL
V0 = 4.2V; XLDP[1:0] = 0
1.5
mA
V0 = 4.2V; XLDP[1:0] = 1
5
V0 = 4.2V; XLDP[1:0] = 2
8
V0 = 4.2V; XLDP[1:0] = 3
25
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