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參數(shù)資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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36
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a source
graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is frequency matched
and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics system and the graphics system
is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively synchronized to the REF input as shown in
Figure 27.
To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input of the
PFD. The reference and feedback dividers are not used.
The output clock frequency is:
total
horizontal
f
HSYNC
CLK
=
The only remaining task is to select a post divider modulus (NPx) that allows the VCO frequency to be within its nominal range.
14.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel clocks
generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by the FS6131 is
set to divide the output clock frequency (fCLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.
Video Graphics System
System HSYNC
Clock In
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider (N
F)
Internal
Loop
Filter
R
LF
C
LF
EXTLF
I2C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
FBKDSRC[1:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
CLK )
(f
CLK )
(f
VCO )
R
IPRG
LOCK/
IPRG
Post
Divider
(N
Px)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
CMOS/PECL
Output
CLKN
(f
CLK )
CLKP
C
LP
Figure 27: Block Diagram: Genlocking
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