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參數(shù)資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大小： | 746K |
| 代理商： | 11274-502-XTD |
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16
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 4: Device Configuration Bits
Name
Description
REFDSRC
(Bit 12)
Reference Divider Source
Bit = 0
Crystal oscillator (VCXO)
Bit = 1
REF pin
SHUT
(Bit 13)
Main Loop Shut Down Select
Bit = 0
Disabled (main loop operates)
Bit = 1
Enabled (main loop shuts down)
PDREF
(Bit 14)
Phase Detector Reference Source
Bit = 0
Reference divider
Bit = 1
REF pin
PDFBK
(Bit 15)
Phase Detector Feedback Source
Bit = 0
Feedback divider
Bit = 1
FBK pin
FBKDSRC[1:0]
(Bits 39-38)
Feedback Divider Source
Bit 39 = 0
Bit 38 = 0
Post divider output
Bit 39 = 0
Bit 38 = 1
FBK pin
Bit 39 = 1
Bit 38 = 0
VCO output (post divider input)
Bit 39 = 1
Bit 38 = 1
FBK pin
EXTLF
(Bit 42)
External Loop Filter Select
Bit = 0
Internal loop filter
Bit = 1
EXTLF pin
OSCTYPE
(Bit 45)
Oscillator Type
Bit = 0
Low phase jitter oscillator
Bit = 1
FS6031 compatible oscillator
OUTMUX[1:0]
(Bits 47-46)
Output Multiplexer Select
Bit 47 = 0
Bit 46 = 0
Main loop PLL (VCO output)
Bit 47 = 0
Bit 46 = 1
Reference divider output
Bit 47 = 1
Bit 46 = 0
Phase detector input
Bit 47 = 1
Bit 46 = 1
VCXO output
GBL
(Bit 48)
Clock Gobbler Control
Bit = 0
No clock phase adjust
Bit = 1
Clock phase adjust
CMOS
(Bit 60)
CLKP/CLKN Output Mode
Bit = 0
PECL output
(positive-ECL output drive)
Bit = 1
CMOS output/
lock status indicator
Table 5: LOCK/IPRG Pin Configuration Bits
Name
Description
STAT[1:0]
(Bits 63-62)
Crystal Loop Lock STATus Mode/
Main Loop Phase Align STATus Mode (see also Table 6)
Bit 63 = 0
Bit 62 = 0
Crystal loop lock status:
locked or unlocked
Bit 63 = 0
Bit 62 = 1
Crystal loop lock status:
out-of-range high or low
Bit 63 = 1
Bit 62 = 0
Main loop phase align status
Bit 63 = 1
Bit 62 = 1
Feedback divider output
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