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參數(shù)資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 746K |
| 代理商： | 11274-502-XTD |
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17
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Table 6: Lock Status
CMOS
STAT[1]
STAT[0]
LOCK/IPRG Pin
STAT[1] Read
Status
1
0
1
Locked
0
Unlocked
1
0
1
0
Out-of-range: low
1
Out-of-range: high
Table 7: Main Loop Tuning Bits
Name
Description
VCOSPD
(Bit 44)
VCO SPeeD Range Select (see Table 16)
Bit = 0
High speed range
Bit = 1
Low speed range
MLCP[1:0]
(Bits 41-40)
Main Loop Charge Pump Current
Bit 41 = 0
Bit 40 = 0
Current = 1.5
mA
Bit 41 = 0
Bit 40 = 1
Current = 5
mA
Bit 41 = 1
Bit 40 = 0
Current = 8
mA
Bit 41 = 1
Bit 40 = 1
Current = 24
mA
LFTC
(Bit 43)
Loop Filter Time Constant (internal)
Bit = 0
Short time constant: 13.5
ms
Bit = 1
Long time constant: 135
ms
Table 8: Divider Control Bits
Name
Description
REFDIV[11:0]
(Bits 11-0)
REFerence DIVider (NR)
FBKDIV[13:0]
(Bits 37-24)
FeedBacK DIVider (NF)
FBKDIV[2:0]
A-Counter value
FBKDIV[13:3]
M-Counter value
POST1[1:0]
(Bits 17-16)
POST Divider #1 (NP1)
Bit 17 = 0
Bit 16 = 0
Divide by 1
Bit 17 = 0
Bit 16 = 1
Divide by 2
Bit 17 = 1
Bit 16 = 0
Divide by 4
Bit 17 = 1
Bit 16 = 1
Divide by 8
POST2[1:0]
(Bits 19-18)
POST Divider #2 (NP2)
Bit 19 = 0
Bit 18 = 0
Divide by 1
Bit 19 = 0
Bit 18 = 1
Divide by 3
Bit 19 = 1
Bit 18 = 0
Divide by 5
Bit 19 = 1
Bit 18 = 1
Divide by 4
POST3[1:0]
(Bits 21-20)
POST Divider #3 (NP3)
Bit 21 = 0
Bit 20 = 0
Divide by 1
Bit 21 = 0
Bit 20 = 1
Divide by 3
Bit 21 = 1
Bit 20 = 0
Divide by 5
Bit 21 = 1
Bit 20 = 1
Divide by 4
Reserved (0)
(Bits 23 - 22)
Set these reserved bits to 0
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