參數(shù)資料
型號(hào)： 1200
廠商： TEXAS INSTRUMENTS INC
元件分類： 無繩電話/電話
英文描述： TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC20
封裝： 4 X 4 MM, ROHS COMPLIANT, QLP-20
文件頁數(shù)： 13/70頁
文件大?。?/td> 841K
代理商： 1200
Chipcon
SmartRF CC1100
Chipcon AS
SmartRF
CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
Page 20 of 68
power control settings. The SPI expects up to
eight data bytes after receiving the address.
By programming the PATABLE, controlled PA
power ramp-up and ramp-down can be
achieved, as well as ASK modulation shaping
for reduced bandwidth. See section 32 on
page 36 for output power programming details.
The PATABLE is an 8-byte table that defines
the PA control settings to use for each of the
eight PA power values (selected by the 3-bit
value FREND0.PA_POWER). The table is
written to and read from the lowest setting (0)
to the highest (7), one byte at a time. An index
counter is used to control the access to the
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the
highest value is reached the counter restarts at
zero.
The access to the PATABLE is either single
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The read/write bit controls whether
the access is a write access (R/W=0) or a read
access (R/W=1).
If one byte is written to the PATABLE and this
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
Note that the content of the PATABLE is lost
when entering the SLEEP state, except for the
first byte (index 0).
0
A6
A5
A4
A3
A2
A0
A1
D
W
7
D
W
6
D
W
5
D
W
4
D
W
3
D
W
2
D
W
1
D
W
0
1
A6
A5
A4
A3
A2
A0
A1
D
R
7
D
R
6
D
R
5
D
R
4
D
R
3
D
R
2
D
R
1
D
R
0
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO
Hi-Z
t
sp
t
ch
t
cl
t
sd
t
hd
t
ns
X
Hi-Z
X
S7
S6
S5
S4
S3
S2
S1
S0
Hi-Z
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
S7
X
Figure 6: Configuration registers write and read operations
Parameter
Description
Min
Max
FSCLK
SCLK frequency
0
10MHz
tsp,pd
CSn
low to positive edge on SCLK, in power-down mode
TBD
s
-
tsp
CSn
low to positive edge on SCLK, in active mode
TBDns
-
tch
Clock high
50ns
-
tcl
Clock low
50ns
-
trise
Clock rise time
-
TBDns
tfall
Clock rise time
-
TBDns
tsd
Setup data to positive edge on SCLK
TBDns
-
thd
Hold data after positive edge on SCLK
TBDns
-
tns
Negative edge on SCLK to CSn high.
TBDns
-
Table 16: SPI interface timing requirements
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