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參數(shù)資料
| 型號： | 20-101-0358 |
| 廠商： | Rabbit Semiconductor |
| 文件頁數(shù)： | 21/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | COMPUTER SINGLE-BOARD BL1820 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Jackrabbit |
| 模塊/板類型： | 單板計算機(jī)模塊 |
| 適用于相關(guān)產(chǎn)品： | BL1820 |
| 產(chǎn)品目錄頁面： | 618 (CN2011-ZH PDF) |
| 其它名稱： | 316-1081 |
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24
Jackrabbit (BL1800)
It is very easy to do pulse-width modulation with the Rabbit 2000 microprocessor because
of the chip’s architecture.
3.4.1 DA1
The op amp supporting DA1 converts pulse-width modulated signals to an analog voltage
between 0 V and 5 V. A digital signal that varies with time is fed from PD4. The resolution
of the DA1 output depends on the smallest increment of time to change the on/off time
(the time between 5 V and 0 V). The Jackrabbit uses the Rabbit 2000’s Port D control reg-
isters to clock out the signal at a timer timeout. The timer used is timer B. Timer B has 10
bits of resolution so that the voltage can be varied in 1/1024 increments. The resolution is
thus about 5 mV (5 V/1024).
R28 is present solely to balance the op amp input current bias. R25 helps to achieve a volt-
age close to ground for a 0% duty cycle.
A design constraint dictates how fast timer B must run. The hardware filter has a resistor-
capacitor filter that averages the 0 V and 5 V values. Its effect is to smooth out the digital
pulse train. It cannot be perfect, and so there will be some ripple in the output voltage. The
maximum signal decay between pulses will occur when DA1 is set to 2.5 V. This means
the pulse train will have a 50% duty cycle. The maximum signal decay will be
where RC = 0.01 s for 14.74 MHz Jackrabbits, and t is the pulse on or off time (not the
length of the total cycle).
Timer B is driven at the Rabbit 2000 frequency divided by 2. The frequency achievable
with a 14.74 MHz clock is (14.74 MHz/2)/1024 = 7.17 kHz. This is a period of 1/f = 139 s.
For a 50% duty cycle, half of the period will be high (70 s at 5 V), and half will be low
(70 s at 0 V). Thus, a 14.74 MHz Jackrabbit has t = 70 s. Based on the standard capaci-
tor discharge formula, this means that the maximum voltage change will be
This is less than a 20 mV peak-to-peak ripple.
The DA1 output can be less than 100 mV for a 0% duty cycle and above 3.5 V for a 100%
duty cycle. Because of software limitations on the low side and hardware limitations on
the high side, the duty cycle can only be programmed from 12% to 72%. The low limita-
tion allows the software to perform other tasks as well as maintain the PWM for the D/A
converters. The high limitation is simply the maximum voltage obtainable with the
LM324 op amp used in the circuit. Anything outside the 12%–72% range gets output as
2.5 V
1
e
t
–
RC
--------
–
×
2.5 V
1
e
70 s
–
0.01 s
----------------
–
×
17.4 mV
=
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