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| 型號： | 20315 |
| 英文描述： | Interfacing the AM29200 RISC Microcontroller to the MACE Am79C940 Ethernet Controller? 28.6KB (PDF) |
| 中文描述： | 接口的AM29200 RISC微控制器的MACE Am79C940的以太網(wǎng)控制器？ 28.6KB（PDF格式） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 28K |
| 代理商： | 20315 |
Publication#
20315
Issue Date:
August 1995
Rev.
A
Amendment
/0
1
Interfacing the Am29200 RISC Microcontroller
to the MACE
TM
Am79C940 Ethernet Controller
Application Note
by Phil Simmons
INTRODUCTION
This report outlines the interface between a Am29200
RISC microcontroller and a MACE Am79C940 Ethernet
controller to address embedded applications. This
solution targets system cost and shows a simple glue-
less interface that can significantly reduce hardware de-
sign time. The 29K series of microprocessors and
microcontrollers are completely software compatible
and hence enables a designer to visualize a range of
products without having to re-invest major programming
resources for every level of processor performance.
AM29200 RISC MICROCONTROLLER
The Am29200 microprocessor is the first in a line of
RISC microcontrollers based on the 29K architecture
that targets systems that do not require the extremely
high performance of other 29K microprocessors, but
needs very low system cost made possible by the
integration of processor, certain peripherals and sup-
port logic. The on-chip functions include: a ROM control-
ler, a DRAM controller, a Peripheral Interface Adapter,
a DMA controller, a Programmable I/O Port, a Parallel
Port, a Serial Port, a Video Interface, and an
Interrupt Controller.
The solution shown in this application note provides a
minimal interface between the Am29200 RISC
microcontroller and the Am79C940 MACE Network In-
terface Controller using the DMA facilities integrated
into the Am29200.
MACE AM79C940 ETHERNET
CONTROLLER
The Media Access Controller for Ethernet (MACE) is a
LAN controller designed for a system with centralized or
system specific DMA facilities. The controller has a high
speed 16 bit slave register based interface where all
transfers to or from the system are performed using sim-
ple read and write cycles.
The MACE provides an IEEE 802.3 interface that may
be tailored to a specific application. It provides a com-
plete Ethernet node solution with integrated 10BASE-T
transceiver and supports up to 25 MHz system clocks.
The Am79C940 embodies the Media Access Control
(MAC) and Physical Layer Signaling (PLS) sub-layers of
the IEEE 802.3 standard, and provides an IEEE defined
Attachment Unit Interface (AUI) for coupling to an exter-
nal Medium Attachment Unit (MAU).
Additional features also enhance over-all system de-
sign. The individual transmit and receive FIFOs opti-
mize system overhead, providing substantial latency
during packet transmission and reception, and minimiz-
ing intervention during normal network error recovery.
The integrated Manchester encoder/decoder eliminates
the need for an external Serial Interface Adapter (SIA) in
the node system.
HARDWARE DESIGN
The objective of this design was to produce a processor-
ethernet controller interface requiring minimal addi-
tional support logic, but also providing the performance
expected from ethernet.
Memory Support
The memory support required to implement this ether-
net engine is both ROM and RAM based. The ROM of
choice is the Am29F010 Flash EPROM, although
read-only PROMs are equally applicable if field code up-
dates are not necessary. This 5 V only device provides
128 KBytes of memory used primarily for instructions
and parameters. The organization of this device is 8 bits
wide and if the designer arranges 4 devices together to
produce a 32 bit wide image then 512 KBytes provides
both sufficient space to run real-world applications as
well as the 32 bit bus width that provides an efficient
code interface for the processor. If 90 ns devices are
used, then the processor will perform 2 cycle access to
the ROM.
DRAM is required as the destination of the ethernet
packets from the network. The Am29200 currently pro-
vides an interface that will burst 3 cycles for an initial ac-
cess to a page, followed by 2 cycles for all subsequent
accesses to that page. This uses readily available
100 ns fast page mode DRAMs and requires no support
logic for control.
DMA Options
The Am29200 provides either hardware or software op-
tions for producing a DMA engine that will transfer an
ethernet packet between the MACE and DRAM.
Software DMA
The 29K family of RISC microprocessors provides two
special instructions, load multiple (LOADM) and store
multiple (STOREM). These instructions provide the abil-
ity to transfer up to 192 data words between on-chip
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