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| 型號(hào)： | 20315 |
| 英文描述： | Interfacing the AM29200 RISC Microcontroller to the MACE Am79C940 Ethernet Controller? 28.6KB (PDF) |
| 中文描述： | 接口的AM29200 RISC微控制器的MACE Am79C940的以太網(wǎng)控制器？ 28.6KB（PDF格式） |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 28K |
| 代理商： | 20315 |
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AMD
Interfacing the Am29200 RISC Microcontroller to the MACE Am79C940 Controller
5
Bus Utilization
Bytes to be transferred to/from Host (includes header and frame status)
Transfers for 16 bit data bus (4 bytes frame status requires byte access)
Clocks per DMA transfer MACE read/write
Clocks per DMA transfer DRAM read/write
Total Clocks per DMA transfer (includes 1 clock DMA turn around)
Total Clocks to DMA minimum size packet
Total Time to DMA minimum size packet @ 16 MHz (60 ns)
Percentage Bus Bandwidth required for packet DMA
Time remaining following minimum size packet transfer
Number of Clocks per instruction (execution from FLASH memory)
Time per 29200 instruction
Number of instructions that can be executed in 50.88
μ
s
64
34
4
3
8
272
16.32
μ
s
24.29%
50.88
μ
s
2
120 ns
424
As all Am29200 instructions execute in a single clock cy-
cle (except LOADM, STOREM, and IRET) we can esti-
mate the number of instructions available to perform a
real world application while still operating at full ethernet
wire speed.
The 424 instructions figure is a quick estimate that can
be expanded to include such things a interrupt latency,
or refresh overhead, and gain an accurate number of
instructions available to the programmer while writing
driver code.
CONCLUSIONS
The design shown here displays the ease of developing
real world solutions with the Am29200 microcontroller.
Performance can be quickly estimated due to the single
clock per instruction execution unit for all members of
the 29K family.
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