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| 型號： | 20315 |
| 英文描述： | Interfacing the AM29200 RISC Microcontroller to the MACE Am79C940 Ethernet Controller? 28.6KB (PDF) |
| 中文描述： | 接口的AM29200 RISC微控制器的MACE Am79C940的以太網(wǎng)控制器？ 28.6KB（PDF格式） |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 28K |
| 代理商： | 20315 |
AMD
Interfacing the Am29200 RISC Microcontroller to the MACE Am79C940 Controller
4
FIFO Configuration (FIFOCC)
The Transmit and Receive FIFO Watermarks are set to
the minimum values (XMTFW = 8 cycles, RCVFW = 16
bytes) so that the processor can commence DMA as
soon as possible. The update bits are set, in order that
the watermarks can be modified. The Transmit and Re-
ceive Burst flags are set to enabled these functions.
Interrupt Mask (IMR)
All interrupts are masked until initialization is complete.
PLS Configuration (PLSCC)
The 10BASE-T port is selected, but it can be overridden
as the PHYCC register will set automatic port selection.
PHY Configuration
The Link Test, Auto Polarity Correction, and Auto Port
Selection are all enabled.
Internal Address (IAC)
Set the Address Change. If multicast addressing is per-
mitted, then the LOGADDR bit is set and the access is
followed by 8 write cycles to the Logical Address register
(LADRF), else the PHYADDR bit is set and the access is
followed by 6 writes to update the Physical Address
register (PADR).
Logical or Physical Addressing
The Logical Address Register requires a 64 bit mask,
and is updated by performing 8 bytes writes, least sig-
nificant to most significant. The Physical Address
Register is accessed in the same manner except only 48
bits are required through 6 byte write cycles.
MAC Configuration (MACCC)
The transmit and receive functions are enabled by ac-
cessing this register.
PERFORMANCE
Ethernet performance is normally defined by the ability
to transfer 64 byte ethernet packets at full wire speed as
this requires highest system performance.
Ethernet will transfer packets at 10 Mb/s. For this exam-
ple the minimum packet size is defined as 72 bytes (64
bytes of information and 8 bytes of synchronization)
and the interpacket gap will be 9.6
μ
s. Using these
parameters the CPU must process 14880 packets
every second.
Minimum Size Packet CPU
Ethernet Packet
IEEE 802.3 Packet
Bits
62
2
48
48
16
368
32
576
57.6
9.6
67.2
14880
Bytes
7.75
.25
6
6
2
46
4
72
Bits
56
8
48
48
16
368
32
576
Bytes
7
1
6
6
2
46
4
72
Preamble
Synchronization
Destination Address
Source Address
Type
Data
Checksum
Total
Time (
μ
s) @ 10Mb/s
Inter-Packet-Gap (
μ
s)
Total Packet Time (
μ
s)
Packets per second
Preamble
Synchronization
Destination Address
Source Address
Length
Data
Checksum
Total
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