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參數(shù)資料
| 型號： | 20315 |
| 英文描述： | Interfacing the AM29200 RISC Microcontroller to the MACE Am79C940 Ethernet Controller? 28.6KB (PDF) |
| 中文描述： | 接口的AM29200 RISC微控制器的MACE Am79C940的以太網(wǎng)控制器？ 28.6KB（PDF格式） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 28K |
| 代理商： | 20315 |
AMD
Interfacing the Am29200 RISC Microcontroller to the MACE Am79C940 Controller
2
registers and memory structures with a single com-
mand. This can produce a highly efficient DMA engine
under complete control of the software kernel, but can
also be interrupted by a higher priority task.
Hardware DMA
The Am29200 provides two on-chip DMA channels. The
designer can configure one channel to receive packets
and the other to transmit packets (Note that a printer ap-
plication does not necessarily require a DMA channel
for transmit as almost all traffic is received and a trans-
mit packet can be pre-loaded into the large MACE FIFO
before being instructed to transmit).
In order to give minimum code development time while
meeting the performance requirements of ethernet full-
wire speed (see Performance), the design uses the
hardware DMA channels of the Am29200. DMA channel
0 is set for the receive queue and DMA channel 1 for the
transmit queue. When a frame is ready to be transmit-
ted, the DMA channel is configured to transfer the com-
plete frame less one 16-bit word. When the transfer has
completed, the last word is written to the MACE FIFO by
a simple STORE command with the EOF flag set to indi-
cate end of frame. The receive transfer count is set to
maximum and runs freely until the frame is completely
received into DRAM at which point the MACE will
indicate that the last byte of the frame has been trans-
ferred with the EOF signal which terminates the DMA by
connecting to the TDMA input to the Am29200
DMA controller.
MACE Interface
The MACE is set to run at 16 MHz even though the de-
vice can operate at 25 MHz. This is so that the interface
is synchronous and so that no external logic is required.
The SCLK for the MACE is therefore driven from the
Am29200 MEMCLK output. The MACE can be pro-
grammed to operate from either the rising or falling
edges. The Am29200 requires valid data with respect to
rising clock edges and therefore EDSEL is tied to
ground on the MACE.
The MACE is connected to the peripheral port of the
Am29200. As DMA channel 0 and 1 are used and are
both connected to the FIFO chip select for the MACE
(
FDS
), the
PIACS
(0,1) signals must be ANDed to pro-
vide the FIFO select, and the register select for the
MACE (
CS
) can be directly connected to
PIACS2
.
Even though there is an output enable from the
Am29200 specifically for peripheral interfaces, the
normal read/write signal (R/W) is used to meet
timing requirements.
The
RDTREQ
and
TDTREQ
DMA requests issued by
the MACE are connected to the
DREQ
(1-0) signals of
the Am29200 (Channel 0 for receive and channel 1 for
transmit queues). End of Frame (
EOF
) is connected to
TDMA though an inverting gate for receive cycles, and
from a PIO output through an open collector gate for
transmit cycles.
Ethernet Interface
The MACE incorporates both AUI and 10BASE-T stan-
dard interfaces. The AUI interface can be used to pro-
vide 10BASE-2 connectivity by using an external
transceiver. The 10BASE-T interface simply requires
the external filter/transformer and 6 resistors for protec-
tion of the MACE from the twisted-pair connection to the
outside world.
System Power Requirements
The system power requirements are especially low for
this design as the Am29200 is highly integrated and the
addition of support logic is minimal. The MACE incorpo-
rates three modes of sleep, and can be remotely or auto-
matically awoken. When the MACE is completely
asleep the device typically requires 10
μ
A, when dozing
requires typically 3 mA, and when fully operational re-
quires typically 40 mA. The Am29200 can initiate power
savings for the MACE by register updates and hardware
control of the SLEEP pin which is connected to a PIO
output signal.
Timing Diagrams
The synchronous cycles required for transfers is
programmable for both the Am29200 and the
MACE devices.
The peripheral interface on the Am29200 that the MACE
connects to is programmed using software. An
Am29200 peripheral read cycle can be achieved in 3
clocks and a write cycle in 4 clocks. This design there-
fore sets the transfer rate as 4 clocks for the Am29200
so that read and write transfers are the same.
The transfer timing for the MACE is determined by the
status of an external pin (TC). This is tied to ground so
that the MACE is configured to transfer in 3 clock cycles.
The number for the Am29200 and the MACE differ be-
cause the initial Am29200 clock cycle is used to estab-
lish addresses before asserting the appropriate
peripheral chip select.
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