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參數(shù)資料
| 型號(hào)： | 2032VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | 3.3在系統(tǒng)可編程高密度PLD的超快⑩ |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 179K |
| 代理商： | 2032VE |
Specifications
ispLSI 2032VE
5
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
4. -225 speed grade supercedes earlier -200. All parameters other than fmax (internal) are the same.
Table 2-0030A/2032VE
1
4
3
2
1
( )
DESCRIPTION
#
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
ns
ns
MHz
–
–
–
A
–
4
5
6
7
8
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
MHz
MHz
ns
ns
ns
–
A
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay, ORP Bypass
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
–
–
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
ns
ns
-225
MIN. MAX.
–
–
225
4.0
6.0
–
–
–
–
–
0.0
3.5
–
0.0
–
3.5
–
–
–
–
2.0
2.0
–
–
154
250
2.5
3.0
–
–
4.0
–
5.0
–
7.0
7.0
3.5
3.5
-180
MIN. MAX.
–
–
180
5.0
7.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
125
200
3.0
0.0
4.0
0.0
4.0
2.5
2.5
4.0
5.0
6.0
10.0
10.0
5.0
5.0
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