- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371362 > 2096VE (Lattice Semiconductor Corporation) 3.3V In-System Programmable SuperFAST⑩ High Density PLD PDF資料下載
參數(shù)資料
| 型號： | 2096VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | 3.3在系統(tǒng)可編程超快⑩高密度可編程邏輯器件 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 160K |
| 代理商： | 2096VE |
Specifications
ispLSI 2096VE
2
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5V signal levels to
support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VE device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
A0
A3
A1
A2
B7
B4
B6
B5
O
O
I
I
Global
Routing
Pool
(GRP)
C
C
C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
T
T
I
I
I
I
I
I
I
I
I
I
I
I
Y
Y
Y
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
TDI/IN 0
TMS/IN 1
RESET
BSCAN
G
G
I
I
I
I
I
I
I
I
I
I
I
I
Input Bus
0917/2096VE
Megablock
C7
C6
C5
C4
A4
A5
A6
A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
B0
B1
B2
B3
Output Routing Pool (ORP)
C3
C2
C1
C0
Output Routing Pool (ORP)
Input Bus
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Generic Logic
Blocks (GLBs)
Functional Block Diagram
Figure 1. ispLSI 2096VE Functional Block Diagram
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 2096VL | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 2097152 | 32-BIT DYNAMIC RAM MODULE |
| 209CNQ | SCHOTTKY RECTIFIER |
| 209CNQ135 | SCHOTTKY RECTIFIER |
| 209CNQ150 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 2096VL | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 2097 | 功能描述:支架與墊片 SS 1.625 M/F THRD RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc |
| 209-701 | 制造商:WAGO Innovative Connections 功能描述:MARKER PLAIN 制造商:WAGO Innovative Connections 功能描述:MARKER CARD VERTICAL BLANK PK100 制造商:WAGO 功能描述:MARKER CARD, VERTICAL, BLANK, PK100 制造商:WAGO 功能描述:ROHS 制造商:WAGO Innovative Connections 功能描述:TERMINAL BLOCK MARKER, BLANK, WHT, 4MM; Label Type:Legend; Background Color:White; Pack Quantity:100; Accessory Type:Terminal Block Marker; For Use With:Terminal Blocks; Legend:Blank (No Legend); Series:WSB ;RoHS Compliant: Yes |
| 209-701/000-002 | 制造商:WAGO Innovative Connections 功能描述:MARKER PLAIN VERT-YELLOW |
| 209-701/000-005 | 制造商:WAGO Innovative Connections 功能描述:MARKER PLAIN VERT-RED |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。