20
Decoupling and Layout Recommendations
Mobile AMD-K6
Processor Power Supply Design
22495C/0—May 1999
Decoupling Capacitance and Component Placement
The high-frequency decoupling capacitors (C5–C31 in Figure 12
on page 22) should be located as close to the processor power
and ground pins as possible. To minimize resistance and
inductance in the lead length, the use of surface mounted
capacitors is recommended. When possible, use traces to
connect capacitors directly to the processor’s power and ground
pins. The decoupling capacitors can be placed in the Socket 7
cavity on the same side of the processor (component side) or the
opposite side (bottom side).
Suggested component placement for the decoupling capacitors
are shown in Figure 12 on page 22 for CPGA packages and in
Figure 13 on page 23 for CBGA packages. The values of the
capacitors are specified in Table 4 on page 24. Capacitor
recommendations are shown in Table 5 on page 24. The split
voltage planes should be isolated if they are in the same layer of
the circuit board. To separate the two power planes, an isolation
region with a minimum width of 0.254mm is recommended. The
ground plane should never be split.
These recommendations are based on single-sided component
assembly and space constraints. The designer should assume
these are minimum requirements. If double-sided component
assembly is used, it is preferable to use more capacitors of a
smaller value, which reduces the total ESR and total ESL of the
capacitors. For example, instead of four 470-
μ
F capacitors, use
ten 47-
μ
F capacitors. (Check the device specifications shown in
Table 2 on page 20. Occasionally a lower value capacitance has
a higher ESR.) As the effective ESR is lowered, the total
required capacitance is reduced. The breakdown voltage and
case size both affect the ESR value.
Table 2.
Representative ESR Values
Capacitance
470
μ
F
270
μ
F
100
μ
F
68
μ
F
47
μ
F
Device 1
55 m
70 m
90 m
95 m
120 m
Device 2
100 m
100 m
100 m
100 m
250 m