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參數(shù)資料
| 型號： | 240VA |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable 3.3V Generic Digital CrosspointTM |
| 中文描述： | 在系統(tǒng)可編程3.3V的通用數(shù)字CrosspointTM |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 324K |
| 代理商： | 240VA |
13
Specifications
ispGDX240VA
ADVANCED
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
-4
-7
PARAMETER #
Inputs
t
io
GRP
t
grp
MUX
t
muxd
t
muxexp
t
muxs
t
muxsio
t
muxsg
t
muxselexp
Register
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
cesu
t
ceh
Data Path
t
fdbk
t
iobp
t
ioob
t
muxcg
t
muxcio
t
iodg
t
iodio
Outputs
t
ob
t
obs
t
oeen
t
oedis
t
goe
t
toe
Clocks
t
ioclk
t
gclk
t
gclkeng
t
gclkenio
t
ioclkeng
t
gr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
DESCRIPTION
1
MIN. MAX. MIN. MAX. UNITS
32
Input Buffer Delay
—
0.4
—
0.9
ns
33
GRP Delay
—
1.1
—
1.1
ns
34
35
36
37
39
I/O Cell MUX A/B/C/D Data Delay
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
I/O Cell MUX Data Select Expander Delay
—
—
—
—
—
—
1.0
1.5
1.0
1.5
1.5
1.5
—
—
—
—
—
—
1.5
2.0
1.5
3.0
2.0
2.0
ns
ns
ns
ns
ns
ns
40
41
42
43
44
45
46
I/O Latch Delay
I/O Register Setup Time Before Clock
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
I/O Clock Enable Hold Time After Clock
—
—
—
—
—
—
—
1.0
0.8
1.7
1.2
1.0
2.3
0.2
—
—
—
—
—
—
—
1.0
2.0
1.5
0.5
1.5
2.0
0.5
ns
ns
ns
ns
ns
ns
ns
47
48
49
50
51
52
53
I/O Register Feedback Delay
I/O Register Bypass Delay
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
I/O Register I/O MUX Delay (I/O Clock)
—
—
—
—
—
—
—
0.6
0.0
0.0
1.5
1.5
3.5
3.5
—
—
—
—
—
—
—
0.9
0.0
0.0
2.0
3.0
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
54
55
56
57
58
59
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
—
—
—
—
—
—
1.0
4.5
3.5
3.5
0.0
2.5
—
—
—
—
—
—
1.5
6.5
4.0
4.0
0.0
2.0
ns
ns
ns
ns
ns
ns
60
61
62
63
64
I/O Clock Delay
Global Clock Delay
Global Clock Enable (Yx Clock)
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
—
—
—
—
—
0.3
1.3
1.5
1.0
0.5
—
—
—
—
—
2.0
2.0
2.5
3.5
2.5
ns
ns
ns
ns
ns
65
Global Reset to I/O Register Latch
—
6.0
—
11.0
ns
Internal Timing Parameters
1
Over Recommended Operating Conditions
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