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參數(shù)資料
| 型號： | 240VA |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable 3.3V Generic Digital CrosspointTM |
| 中文描述： | 在系統(tǒng)可編程3.3V的通用數(shù)字CrosspointTM |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 324K |
| 代理商： | 240VA |
19
Specifications
ispGDX240VA
Update DR
Clock DR
Shift DR
Boundary Scan
The ispGDXV/VA devices provide IEEE1149.1a test
capability and ISP programming through a standard
Boundary Scan Test Access Port (TAP) interface.
The boundary scan circuitry on the ispGDXVA Family
operates independently of the programmed pattern. This
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
The ispGDXVA devices are identified by the 32-bit JTAG
IDCODE register. The device ID assignments are listed
in Table 4.
Table 3. I/O Shift Register Order
Figure 10. Boundary Scan Register Circuit for I/O Pins
Normal
Function
OE
EXTEST
SCANOUT
(to next cell)
SCANIN
(from previous
cell
Normal
Function
TOE
D
Q
D
Q
D
Q
D
Q
D
Q
I/O Pin
Reset
BSCAN
Registers
BSCAN
Latches
HIGHZ
0
1
0
1
PROG_MODE
EXTEST
I/O Shift Reg Order/ispGDXVA
ispGDX240VA
TDI, TOE, Y2, Y3,
RESET
, Y1, Y0, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, TDO
I/O SHIFT REGISTER ORDER
DEVICE
Table 4. ispGDX240VA Device ID Codes
ID Code/GDX240VA
ispGDX240VA
0001, 0000, 0011, 0101, 0100, 0000, 0100, 0011
32-BIT BOUNDARY SCAN ID CODE
DEVICE
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