參數(shù)資料
型號： 25C128
廠商： Microchip Technology Inc.
英文描述： 128K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,128K位,SPI總線串行EEPROM)
中文描述： 128K的5.0V SPI總線串行EEPROM（4.5?5.5V的，128K的位和SPI總線串行EEPROM的）
文件頁數(shù)： 15/170頁
文件大?。?/td> 4191K
代理商： 25C128
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 13
PIC16F62X
3.0
MEMORY ORGANIZATION
3.1
Program Memory Organization
The PIC16F62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 1K x 14 (0000h - 03FFh) for the PIC16F627
and 2K x 14 (0000h - 07FFh) for the PIC16F628 are
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space (PIC16F627) or 2K x 14 space
(PIC16F628). The RESET vector is at 0000h and the
interrupt vector is at 0004h (Figure 3-1).
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK
3.2
Data Memory Organization
The data memory (Figure 3-2) is partitioned into four
banks, which contain the general purpose registers and
the Special Function Registers (SFR). The SFR’s are
located in the first 32 locations of each Bank. Register
locations 20-7Fh, A0h-FFh, 120h-14Fh, 170h-17Fh
and 1F0h-1FFh are general purpose registers
implemented as static RAM.
The Table below lists how to access the four banks of
registers:
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
3.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 224 x 8 in the
PIC16F62X. Each is accessed either directly or
indirectly through the File Select Register FSR (See
Section 3.4).
PC<12:0>
13
000h
0004
0005
03FFh
1FFFh
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
Interrupt Vector
On-chip Program
Memory
PIC16F627
and
PIC16F628
CALL, RETURN
RETFIE, RETLW
07FFh
PIC16F628
only
On-chip Program
Memory
RP1
RP0
Bank0
0
0
Bank1
0
1
Bank2
1
0
Bank3
1
1
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PDF描述
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