參數(shù)資料
型號： 25C128
廠商： Microchip Technology Inc.
英文描述： 128K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,128K位,SPI總線串行EEPROM)
中文描述： 128K的5.0V SPI總線串行EEPROM（4.5?5.5V的，128K的位和SPI總線串行EEPROM的）
文件頁數(shù)： 57/170頁
文件大?。?/td> 4191K
代理商： 25C128
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 55
PIC16F62X
The code example in Example 9-1 depicts the steps
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 9-1:
INITIALIZING
COMPARATOR MODULE
9.2
Comparator Operation
A single comparator is shown in Figure 9-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at V
IN
+ is less
than the analog input V
IN
-, the output of the comparator
is a digital low level. When the analog input at V
IN
+ is
greater than the analog input V
IN
-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 9-2 represent
the uncertainty due to input offsets and response time.
9.3
Comparator Reference
An external or internal reference signal may be used
depending on the Comparator Operating mode. The
analog signal that is present at V
IN
- is compared to the
signal at V
IN
+, and the digital output of the comparator
is adjusted accordingly (Figure 9-2).
FIGURE 9-2:
SINGLE COMPARATOR
9.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the
comparators operate from the same or different
reference sources. However, threshold detector
applications may require the same reference. The
reference signal must be between V
SS
and V
DD
, and
can be applied to either pin of the comparator(s).
9.3.2
INTERNAL REFERENCE SIGNAL
The Comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 10.0, Voltage Reference Manual,
contains a detailed description of the Voltage Refer-
ence module that provides this signal. The internal
reference signal is used when the comparators are in
mode CM<2:0>=010 (Figure 9-1). In this mode, the
internal voltage reference is applied to the V
IN
+ pin of
both comparators.
9.4
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise the
maximum delay of the comparators should be used
(Table 17-1
).
FLAG_REG EQU
CLRF
CLRF
MOVF
ANDLW
IORWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
0X20
;Init flag register
;Init PORTA
;Load comparator bits
;Mask comparator bits
;Store bits in flag register
;Init comparator mode
;CM<2:0> = 011
;Select Bank1
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
;Select Bank 0
;10
μ
s delay
;Rea
d
CMCO
N
t
o
en
d
chang
e
condition
;Clear pending interrupts
;Select Bank 1
;Enable comparator interrupts
;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE
;Global interrupt enable
FLAG_REG
PORTA
CMCON, W
0xC0
FLAG_REG,F
0x03
CMCON
STATUS,RP0
0x07
TRISA
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
STATUS,RP0
DELAY10
CMCON,F
PIR1,CMIF
STATUS,RP0
PIE1,CMIE
STATUS,RP0
–
+
Vi
N
+
V
IN
-
Result
Result
V
IN
-
V
IN
+
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