參數(shù)資料
型號(hào)： 25C128
廠商： Microchip Technology Inc.
英文描述： 128K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,128K位,SPI總線串行EEPROM)
中文描述： 128K的5.0V SPI總線串行EEPROM（4.5?5.5V的，128K的位和SPI總線串行EEPROM的）
文件頁數(shù)： 97/170頁
文件大?。?/td> 4191K
代理商： 25C128
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 95
PIC16F62X
14.2.6
INTERNAL 4 MH
Z
OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz
(nominal) system clock at V
DD
= 5V and 25
°
C, see
“Electrical Specifications” section for information on
variation over voltage and temperature.
14.2.7
CLKOUT
The PIC16F62X can be configured to provide a clock
out signal by programming the configuration word. The
oscillator frequency, divided by 4 can be used for test
purposes or to synchronize other logic.
14.3
Special Feature: Dual Speed
Oscillator Modes
A software programmable Dual Speed Oscillator mode
is provided when the PIC16F62X is configured in either
ER or INTRC Oscillator modes. This feature allows
users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz. In ER mode, the 4 MHz
setting will vary depending on the value of the external
resistor. Also in ER mode, the 37 kHz operation is fixed
and does not vary with resistor value. Applications that
require low current power savings, but cannot tolerate
putting the part into SLEEP, may use this mode.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 3.2.2.6, Register 3-4.
14.4
RESET
The PIC16F62X differentiates between various kinds of
RESET:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during SLEEP
d)
WDT Reset (normal operation)
e)
WDT Wake-up (SLEEP)
f)
Brown-out Detect (BOD)
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset, MCLR Reset, WDT
Reset and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, since this is viewed as the
resumption of normal operation. TO and PD bits are set
or cleared differently in different RESET situations as
indicated in Table 14-5. These bits are used in software
to determine the nature of the RESET. See Table 14-8
for a full description of RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-6 for pulse width
specification.
FIGURE 14-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
RESET
MCLR/
V
PP
Pin
V
DD
OSC1/
CLKIN
Pin
WDT
Module
V
DD
rise
detect
OST/PWRT
WDT
Timeout
Reset
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple-counter
Enable OST
Enable PWRT
SLEEP
See Table 14-4 for timeout situations.
Note
1:
This is a separate oscillator from the INTRC/ER oscillator.
Brown-out
Detect Reset
BODEN
10-bit Ripple-counter
Q
Schmitt Trigger Input
On-chip
(1)
OSC
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