參數(shù)資料
型號： 25C128
廠商： Microchip Technology Inc.
英文描述： 128K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,128K位,SPI總線串行EEPROM)
中文描述： 128K的5.0V SPI總線串行EEPROM（4.5?5.5V的，128K的位和SPI總線串行EEPROM的）
文件頁數(shù)： 91/170頁
文件大小： 4191K
代理商： 25C128
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 89
PIC16F62X
13.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 13-1:
DATA EEPROM READ
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
; Bank 1
;
; Address to read
; EE Read
; W = EEDATA
; Bank 0
13.4
WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 13-2:
DATA EEPROM WRITE
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
STATUS, RP0
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; Bank 1
; Enable write
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit
; begin write
; Enable INTs
.
INTCON, GIE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
cause the data not to be written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
13.5
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-3:
WRITE VERIFY
BSF STATUS, RP0
MOVF EEDATA, W
BSF EECON1, RD
; Bank 1
; Read the
; value written
;
; Is the value written (in W reg) and
; read (in EEDATA) the same
;
SUBWF EEDATA, W
BCF
STATUS, RP0
BTFSS STATUS, Z
GOTO WRITE_ERR
:
:
;
; Bank0
; Is difference 0
; NO, Write error
; YES, Good write
; Continue program
13.6
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(72
EEPROM write.
ms
duration)
prevents
The write initiate sequence, and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
13.7
DATA EEPROM OPERATION
DURING CODE PROTECT
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data
EEPROM.
R
S
相關(guān)PDF資料
PDF描述
25LC128 128K 5.0V SPI Bus Serial EEPROM(2.5~5.5V,128K位,SPI總線串行EEPROM)
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25C080 8K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,3MHz,8K位,10M次可自定時擦寫周期,EEPROM)
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