參數(shù)資料
型號(hào)： 272420-007
廠商： Intel Corp.
英文描述： Intel386 EX Embedded Microprocessor
中文描述： 英特爾386防爆嵌入式微處理器
文件頁(yè)數(shù)： 20/56頁(yè)
文件大?。?/td> 766K
代理商： 272420-007
Intel386 EX Embedded Microprocessor
20
Datasheet
recognize either an active-high level or a positive transition on the interrupt request lines. An
internal Priority Resolver decides which pending interrupt request (if more than one exists) is the
highest priority, based on the programmed operating mode. The Priority Resolver controls the
single interrupt request line to the CPU. The Priority Resolver’s default priority scheme places the
master interrupt controller’s IR0 as the highest priority and the master’s IR7 as the lowest. The
priority can be modified through software.
Besides the ten interrupt request inputs available to the Intel386 EX microprocessor, additional
interrupts can be supported by cascaded external 8259A modules. Up to four external 8259A units
can be cascaded to the master through connections to the INT3:0 pins. In this configuration, the
interrupt acknowledge (INTA#) signal can be decoded externally using the ADS#, D/C#, W/R#,
and M/IO# signals.
4.4
Timer/Counter Unit
The Timer/Counter Unit (TCU) on the Intel386 EX microprocessor has the same basic
functionality as the industry-standard 82C54 counter/timer. The TCU provides three independent
16-bit counters, each capable of handling clock inputs up to 8 MHz. This maximum frequency
must be considered when programming the input clocks for the counters. Six programmable timer
modes allow the counters to be used as event counters, elapsed-time indicators, programmable one-
shots, and in many other applications. All modes are software programmable.
4.5
Watchdog Timer Unit
The Watchdog Timer (WDT) unit consists of a 32-bit down-counter that decrements every PH1P
cycle, allowing up to 4.3 billion count intervals. The WDTOUT pin is driven high for sixteen
CLK2 cycles when the down-counter reaches zero (the WDT times out). The WDTOUT signal can
be used to reset the chip, to request an interrupt, or to indicate to the user that a ready-hang
situation has occurred. The down-counter can also be updated with a user-defined 32-bit reload
value under certain conditions. Alternatively, the WDT unit can be used as a bus monitor or as a
general-purpose timer.
4.6
Asynchronous Serial I/O Unit
The Intel386 EX microprocessor’s asynchronous Serial I/O (SIO) unit is a Universal
Asynchronous Receiver/ Transmitter (UART). Functionally, it is equivalent to the National
Semiconductor NS16450 and INS8250. The Intel386 EX embedded processor contains two full-
duplex, asynchronous serial channels.
The SIO unit converts serial data characters received from a peripheral device or modem to parallel
data and converts parallel data characters received from the CPU to serial data. The CPU can read
the status of the serial port at any time during its operation. The status information includes the type
and condition of the transfer operations being performed and any errors (parity, framing, overrun,
or break interrupt).
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