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參數(shù)資料
| 型號： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
Datasheet
35
Timer Control Unit (TCU) Inputs
t
107
t
108
t
109
t
110
t
111
TMRCLKn Frequency
8
8
(Unit is MHz)
TMRCLKn Low
60
60
TMRCLKn High
60
60
TMRGATEn High Width
50
50
TMRGATEn Low Width
50
50
t
112
TMRGATEn to TMRCLK Setup
Time (external TMRCLK only)
10
10
t
112a
TMRGATEn to TMRCLK Hold
Time (external TMRCLK only)
11
11
Timer Control Unit (TCU) Outputs
t
113
TMRGATEn Low to TMROUT
Valid
29
32
t
114
Interrupt Control Unit (ICU) Inputs
TMRCLKn Low to TMROUT Valid
29
32
t
115
D7:0 Setup Time
(INTA# Cycle 2)
7
7
t
116
D7:0 Hold Time
(INTA# Cycle 2)
4
4
Interrupt Control Unit (ICU) Outputs
t
117
DMA Unit Inputs
CLK2 High to CAS2:0 Valid
25
28
t
118
DREQ Setup Time
(Sync Mode)
15
15
t
119
DREQ Hold Time
(Sync Mode)
4
4
(2)
t
120
DREQ Setup Time
(Async Mode)
9
9
t
121
DREQ Hold Time
(Async Mode)
9
9
(2)
Table 11. 5-Volt AC Characteristics (Sheet 4 of 5)
Symbol
Parameter
33 MHz
25 MHz
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
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