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| 型號： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 38/56頁 |
| 文件大小： | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
38
Datasheet
t
19
t
19a
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
27a
t
28
t
28a
READY# Setup Time
15
17
BS8# Setup Time
17
19
READY#, BS8# Hold Time
4
4
D15:0 Read Setup Time
9
11
D15:0 Read Hold Time
6
6
HOLD Setup Time
17
22
HOLD Hold Time
5
5
RESET Setup Time
12
13
RESET Hold Time
4
4
NMI Setup Time
16
16
(4)
SMI# Setup Time
16
16
(4)
NMI Hold Time
16
16
(4)
SMI# Hold Time
16
16
(4)
t
29
PEREQ, ERROR#, BUSY#
Setup Time
14
16
(4)
t
30
PEREQ, ERROR#, BUSY#
Hold Time
5
5
(4)
t
31
t
32
t
33
READY# Valid Delay
4
33
4
42
C
L
= 30 pF
READY# Float Delay
4
33
4
42
LBA# Valid Delay
4
31
4
40
t
34
CS6:0#, UCS# Valid Delay
4
33 (34 in
SMM)
4
42
C
L
= 30 pF
t
35
t
36
CLKOUT Valid Delay
4
14
4
18
C
L
= 30 pF
PWRDOWN Valid Delay
4
26
4
29
t
41
A25:1, BHE#, BLE# Valid to
WR# Low
0
0
t
41a
UCS#, CS6:0# Valid to WR#
Low
0
0
t
42
A25:1, BHE#, BLE# Hold
After WR# High
0
0
(6)
Table 12. 3-Volt AC Characteristics (Sheet 2 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
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