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參數(shù)資料
| 型號： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 75/161頁 |
| 文件大?。?/td> | 1832K |
| 代理商： | 28233-11 |
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allocation ranges from 0.8 % to 100 %. Programming a port
’
s rate value to zero
disables transmissions from that port and causes the transmit circuitry to ignore
FIFO flag indications from that port.
The programmed rate value is an upper bound on the transmission from a
particular port, and the exact ratio may not be achieved if multiple ports are active
at the same time.
CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.7 FIFO Port/UTOPIA Interface
100046C
Conexant
2-41
If a higher priority port indicates that it has a cell ready during servicing of a
lower priority port, service switches to the higher priority port after completion of
the cell currently being formatted and transmitted. Servicing of ports and priority
levels continues in this manner until the lowest priority ports are serviced and
empty.
Port priority programming is not intended to be dynamic and should be used
only as a configuration setup. Changes in port priority cannot take place until
ports are inactive (via FIFO empty flag or transmit rate shaping).
Unused ports should be programmed to the lowest priority level, and their
empty flag inputs should be connected to ground.
2.7.3 Transmit Rate Shaping Control
Each of the four transmit data ports has a rate shaping control to allow the
allocation of programmable bandwidth to cells originating from this port. The
TX_RATE_01 [0x09] and TX_RATE_23 [0x08] registers control this function.
The transmit circuitry contains a mod-256 master counter to control rate
shaping. This counter is incremented for every ATM cell that is transmitted, and it
rolls over to 0 when count 255 is reached.
The programmed rate value for a port in the TX_RATE_xx registers
determines the count range for which transmission from that port is allowed. For
instance, if Port 0 is programmed with a rate value of 63, transmission of cells
queued at Port 0 will be allowed for 64 (one more than the programmed value) of
the 256 counts of the master counter.
The transmission is spread over all counts of the counter so that transmission
is not bursty. This gives Port 0 a bandwidth allocation of 25 % of the total
outgoing bandwidth even if all of the other ports are inactive.
This allocation scheme is valid for rate values from 1 to 255 resulting in
2.7.4 Receive Port Addressing
Received cells are routed to each of the four FIFO ports depending on the values
in the Header Value and Header Mask registers. These registers allow a range of
ATM cells to be routed to one of the four FIFO ports. Also, the same ATM cell
can be routed to multiple receive FIFO ports if desired.
The HDR_VALx_12 and HDR_VALx_34 register contents are used to match
incoming ATM cell headers. There are four sets of these registers (x = 0, 1, 2, 3),
one set for each of the four receive FIFO ports. If HDR_VALx_12 and
HDR_VALx_34 are a bitwise match to the incoming cell, then this cell is routed
to the x receive FIFO port.
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