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參數(shù)資料
| 型號(hào)： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 80/161頁 |
| 文件大?。?/td> | 1832K |
| 代理商： | 28233-11 |
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while the data link transmitter reads from the other half of the buffer. This gives
the processor at least 160
μ
s (at the fastest byte rate) to assemble the next four
bytes of message for transmission before the next interrupt is issued. Interrupts
are issued each time the transmitter circuitry reaches a 4-byte buffer boundary.
The transmitter should be initialized with the DL_CTRL_STAT register bits
6
–
0 written to zero. This enables the transmitter to send idle flags on the data link.
No interrupts are generated when the data link is sending idle flags, thus no
processor intervention is required until a message is to be sent.
2.0 Functional Description
CN8223
2.8 FEAC Channel and HDLC Data Link Programming
ATM Transmitter/Receiver with UTOPIA Interface
2-46
Conexant
100046C
The transmitter implements an HDLC data link per ITU standard Q.921. The
functions provided by the data link transmitter circuitry are transparency zero
stuffing, Frame Check Sequence (FCS) generation, idle flag generation, and abort
flag generation. There are no restrictions on the total length of the message.
Q.921 requires that all messages be an integral number of 8-bit bytes. The
transmitter can only transmit 8-bit bytes. The byte transmission times for the
transmitter are approximately those shown in
Table 2-28
.
An 8-byte buffer (organized as four 16-bit words) is provided for the transmit
data link channel
to minimize processor interruptions. This buffer is located at
addresses 0x5C through 0x5F. Byte 0 is the least significant byte of 0x5C, byte 1
is the most significant byte of 0x5C, byte 2 is the least significant byte of 0x5D,
etc. Filling of this buffer is accomplished by the processor in the same manner as
writing to control registers. This buffer can be read as well as written to verify
contents. The buffer is divided into two halves to reduce the real-time
requirements on the processor. The processor loads four bytes (2 words) at a time,
2.8.3.1 Sending a
Message
Beginning with an idle channel, the processor writes the first four bytes of
message data to the TX_DL_BUFFER. The first two bytes of data to be
transmitted should be written to 0x5C. The message is written to the buffer in
ascending order starting at 0x5C and ending at 0x5F. The least significant bit
(LSB) in each byte is transmitted first. This buffer can be written well before the
message is to be sent, if desired. After the first block of data is present in the
buffer memory, the processor writes to the DL_CTRL_STAT register to begin
transmission:
Send Message = 1
TxBytes[2:0] = 3
Send FCS = 0
Abort Message = 0
Table 2-28. Byte Transmission Times for Transmitter
Mode
Byte Transmission Times
DS3 C bit Parity
284
μ
s
G.751 E3
357
μ
s
G.832 E3, E4
125
μ
s
STS-1
125
μ
s
STS-3c/STM-1
42
μ
s
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