
Preliminary N8234DSC
Preliminary Information
This document contains information on a product under development. The parametric information contains target
parameters that are subject to change.
RS8234
ATM ServiceSAR Plus with xBR Traffic Management
The RS8234 Service Segmentation and Reassembly Controller integrates ATM
terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with
service specific functions in a single package. The ServiceSAR Controller generates
and terminates ATM traffic as well as automatically scheduling cells for transmission.
The RS8234 is targeted at 155 Mbps throughput systems where the number of VCCs
is relatively large, or the performance of the overall system is critical. Examples of
such networking equipment include Routers, Ethernet switches, ATM Edge switches,
or Frame Relay switches.
Service-Specific Performance Accelerators
The RS8234 incorporates numerous service-specific features designed to accelerate
and enhance system performance. As examples, the RS8234 implements Echo
Suppression of LAN traffic via LECID filtering, and supports Frame Relay DE to CLP
interworking.
Advanced xBR Traffic Management
The xBR Traffic Manager in the RS8234 supports multiple ATM service categories.
This includes CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed
Frame Rate) and ABR. The RS8234 manages each VCC independently. It dynamically
schedules segmentation traffic to comply with up to 16+CBR user-configured
scheduling priorities for the various traffic classes. Scheduling is controlled by a
Schedule Table configured by the user and based on a user-specified time reference.
ABR channels are managed in hardware according to user programmable ABR
templates. These templates tune the performance of the RS8234’s ABR algorithms to
a specific system’s or network’s requirements.
Distinguishing Features
Service-Specific Performance
Accelerators
LECID filtering and echo
suppression
Dual leaky bucket based on CLP
(frame relay)
Frame relay DE interworking
Internal SNMP MIB counters
IP over ATM; supports both
CLP0+1 and ABR shaping
Flexible Architectures
Multi-peer host
Direct switch attachment via
reverse UTOPIA
ATM terminal
– Host control
– Local bus control
Optional local processor
New Features
3.3 V, 388 BGA lowers power and
eases PCB assembly
AAL3/4 CPCS generation and
checking
PCI 2.1, including support for
serial EEPROM
Enhancements to xBR Traffic
Manager
– fewer ABR templates
– improved CBR tunneling
Reduced memory size for VCC
lookup tables
Increased addressing flexibility
Additional byte lane swappers for
increased system flexibility
-continued-
Functional Block Diagram
Multi-client
PCI Bus
Local Bus
RS8234
PCI
DMA
Local Memory
Control/
Status
Cell
FIFO
Reassembly
Segmentation
CBR, VBR, ABR,
Timer
Counters
Traffic Manager
Patent Pending
Coprocessor
Interface
Master/
Slave
Co-
proc’r
UBR, GFR
Rx/Tx
Master/Slave
UTOPIA
RS8250
PHY
Device