Preliminary N8234DSC
xBR Traffic Management
TM4.0 Service Classes
–CBR
– VBR (single, dual and CLP-
based leaky buckets)
– Real time VBR
–ABR
–UBR
– GFC (controlled & uncon-
trolled flows)
– Guaranteed Frame Rate
(GFR) (guaranteed MCR on
UBR VCCs)
16 Levels of priorities (16 + CBR)
Dynamic per-VCC scheduling
Multiple programmable ABR
templates (supplied by Rockwell
or user)
Scheduler driven by local system
clock for low jitter CBR
Internal RM OAM cell feedback
path
Virtual FIFO rate matching
(Source Rate Matching)
Per-VCC MCR and ICR.
Tunneling
– VP tunnels (VCI interleaving
on PDU boundaries)
– CBR tunnels (cells interleaved
as UBR, VBR or ABR with an
aggregate CBR limit)
Multi-Queue Segmentation Processing
32 transmit queues with optional
priority levels
64 kB VCCs maximum *
AAL5 & AAL3/4 CPCS generation
AAL0 Null CPCS (optional use of
PTI for PDU demarcation)
ATM cell header generation
Raw cell mode (52 octet)
200 Mbps half duplex
155 Mbps full duplex (w/ 2-cell
PDUs)
Variable length transmit FIFO -
CDV - host latency matching (1 to
9 cells)
Symmetric Tx and Rx
architecture
– buffer descriptors
–queues
User defined field circulates back
to the host (32 bits)
Distributed host or SAR shared
memory segmentation
Simultaneous segmentation and
reassembly
Per-PDU control of CLP/PTI
(UBR)
Per-PDU control of AAL5 UU field
Message & streaming status
modes
Virtual Tx FIFO (PCI host)
Multi-Queue Reassembly Processing
32 reassembly queues
64 kB VCCs maximum *
AAL5 & AAL3/4 CPCS checking
AAL0
– PTI termination
– Cell count termination
Early Packet Discard, based on:
– Receive buffer underflow
– Receive status overflow
– CLP with priority threshold
– AAL5 max PDU length
– Rx FIFO full
– Frame relay DE with priority
threshold
– LECID filtering and echo sup-
pression
– Per-VCC firewalls
Dynamic channel lookup (NNI or
UNI addressing)
– Supports full address space
– Deterministic
– Flexible VCI count per VPI
– Optimized for signalling
address assignment
Message and streaming status
modes
Raw cell mode (52 octet)
200 Mbps half duplex
155 Mbps full duplex (w/ 2-cell
PDUs)
Distributed host or SAR shared
memory reassembly
8 Programmable reassembly
hardware time-outs (per-VCC
assignable)
Global max PDU length for AAL5
Per-VCC buffer firewall (memory
usage limit)
Simultaneous reassembly and
segmentation
Idle cell filtering
32 kB duplex VCCs
High Performance Host Architecture
with Buffer Isolation
Write-only control and status
Read multiple command for data
transfer
Up to 32 host clients control and
status queues
Physical or logical clients
– Enables peer-to-peer archi-
tecture
Descriptor-based buffer chaining
Scatter/gather DMA
Endian neutral (allows data word
and control word byte swapping,
for both big and little endian
systems)
Non-word (byte) aligned host
buffer addresses
Automatically detects presence of
Tx data or Rx free buffers
Virtual FIFOs (PCI bursts treated
as a single address)
Hardware indication of BOM
Allows isolation of system
resources
Status queue interrupt delay
Designer Toolkit
Evaluation hardware and
software
Reference schematics
Hardware Programming
Interface - RS823xHPI reference
Source code (C)
Generous Implementation of OAM-PM
Protocols
Detection of all F4/F5 OAM flows
Internal PM monitoring and
generation for up to 128 VCCs
Optional global OAM Rx/Tx
queues
In-Line OAM insertion &
generation
Standards-Based I/O
33 MHz PCI 2.1
Serial EEPROM to store PCI
configuration information
PHY interfaces
– UTOPIA master (Level 1)
– UTOPIA slave (Level 1)
Flexible SAR shared memory
architecture
Optional local control interface
Boundary scan for board-level
testing
Source loopback, for diagnostics
Glueless connection to
Rockwell’s ATM physical layer
device, the RS8250
Standards Compliance
UNI/NNI 3.1
TM 4.0
Bellcore GR-1248
ATM Forum B-ICI V2.0
I.363
I.610 /GR-1248
AToM MIB (RFC1695)
ILMI MIB
ANSI T1.635
GFC per I.361
SNMP
I2C protocol
PCI Revision 2.1
IEEE 1149.1-1990
IEEE 1149.1 Supplement B, 1994
-continued Distinguishing Features-